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Cadence, ARM co-develop multicore ref design kits

Posted: 12 Dec 2007     Print Version  Bookmark and Share

Keywords:multicore processor  reference design  RTL Compiler 

Cadence Design Systems Inc. and ARM have jointly developed reference methodologies, one for the ARM11 MPCore multicore processor and the other for low-power implementation of the ARM1176JZF-S processor, which incorporates ARM Intelligent Energy Manager (IEM) technology. These reference methodologies provide enhanced design solutions to mutual customers designing multicore, low-power devices.

"With the Cadence Low-Power Solution, which includes Encounter RTL Compiler and SoC Encounter GXL, we have been able to exceed performance goals for our ARM processor-based ASIC design efforts," said Ying F. Chang, engineering director, custom SoC solutions engineering, NEC Electronics America. "We applaud the collaboration between ARM and Cadence to deliver flows that will speed and simplify the delivery of lower-power ARM processors."

The ARM11 MPCore multicore processor was the first to feature ARM MPCore multiprocessing technology, which provides a scalable solution for both performance and power management that can address the requirements of multiple designs.

"The reference methodology for the ARM11 MPCore multicore processor provides a high-performance reference flow that offers predictable, low-risk implementation of multiprocessor configurations," said Keith Clarke, VP of technical marketing at ARM. "Both the ARM11 MPCore processor and low-power ARM1176JZF-S processor flows have been pre-validated with ARM Artisan Physical IP in order to optimise the implementation of ARM synthesizable processor IP."

The low-power reference methodology for the ARM1176JZF-S processor provides enhanced features required to support IEM technology, which has been shown to reduce CPU energy consumption by more than 60 per cent, and supports the Dynamic Voltage and Frequency Scaling (DVFS) hardware technique that IEM technology exploits.

The reference methodologies comprehend the Common Power Format (CPF), which enables the up-front specification of power domains, power modes, level shifting and isolation rules to automate advanced low-power design techniques. The methodologies leverage a wide range of products of the Cadence Low-Power Solution, including the Cadence SoC Encounter RTL-to-GDSII system, Encounter RTL Compiler with global synthesis, Encounter Conformal Low Power, and VoltageStorm power rail analysis.

The reference methodologies are planned to be available at the time of the production release of the new processors in 1H 08.

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