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Clocking high-speed A/D converters
Keywords:ADC clock PLL CO converter
Extremely high-speed ADCs demand a low-jitter sample clock in order to preserve SNR. These 8bit and 10bit converters have best-case noise floors set by quantisation noise. In this article, we look at the strategy for optimising the performance of the sample clock based on PLL/VCO characteristics. This means minimising overall integrated phase noise, which minimises clock jitter.
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Related Datasheets
| Part Number | Description | Category |
| • ADC08D1500 | High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter from the PowerWise® Family | Cards and Modules |
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