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Design flow implements DSP algorithm in next-gen design

Posted: 18 Oct 2007     Print Version  Bookmark and Share

Keywords:design flow  FPGA  DSP  synthesis tool 

Mentor Graphics Corp. and Altera have unveiled a design flow that enables users to implement complex DSP algorithms in high-performance FPGAs directly from industry-standard ANSI C++.

The design flow, based on Altera's Accelerated Libraries for Mentor Graphics' Catapult C Synthesis tool, delivers 50-80 per cent DSP Fmax performance improvements, provides a low-effort path to dedicated DSP hardware creation and gives companies a cost-per-channel advantage over expensive, power-hungry discrete DSPs for high-performance applications.

Altera's Accelerated Libraries for Catapult C Synthesis enable the Catapult C Synthesis tool to perform ASIC-like optimisations and advanced, technology-aware scheduling for unique DSP macro IP found in Altera's FPGA technologies. The result is designs that operate 50-80 per cent faster than results previously achieved by any high level synthesis tool. These performance levels even surpass RTL synthesis tools, a unique accomplishment considering the ANSI C++ source is of a much higher abstraction than RTL.

The Catapult C/Altera DSP design solution is a C-to-RTL design flow that closely resembles the traditional DSP software programming flow. In both flows, algorithm designers develop a floating-point model of an algorithm, and then convert that to a fixed-point model, typically in C++. At this point in the traditional flow, software developers compile the C code for an off-the-shelf DSP. With the Catapult C/Altera flow, a hardware designer would use the Catapult C Synthesis tool with Altera's Accelerated Libraries to automatically create a DSP hardware implementation for an Altera FPGA. Unlike before, the hardware designer does not need to manually write the RTL code, worry about hand-coded errors, or re-write RTL code numerous times to find an architecture that delivers reasonable performance. The Catapult C/Altera solution automates the RTL creation process, delivering hardware performance with the flexibility of a DSP software programming flow.

"In addition to being deployed at designing high-end ASICs, Catapult C Synthesis offers numerous productivity advantages for designers who target FPGAs," said Simon Bloch, general manager, design creation and synthesis division, Mentor. "With this partnership, Altera and Mentor Graphics have given our customers a new, efficient choice for implementing high-performance DSP functionality in their next-generation designs."

"Adding our Accelerated Libraries to the Catapult C Synthesis Tool is another important step in our partnership with Mentor Graphics and provides our customers with improved productivity and increased functionality for their designs," said Udi Landen, VP of software and IP engineering at Altera. "The performance improvements that can be realised with the tool further promote the move of adopting FPGAs in a growing number of high-performance DSP applications."

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