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EE Times-India > EDA/IP

PCIe compliance test bench solution debuts

Posted: 18 Oct 2007     Print Version  Bookmark and Share

Keywords:PCIe compliance testing  signal integrity  test bench 

SyntheSys Research Inc. has released the BERTScope PCIe Test Bench, which the company says is the first complete solution for PCIe transmitter and receiver PHY compliance testing at 2.5- and 5GTps rates.

Built on the BERTScope S signal integrity analyser platform, new capabilities have been added for 5 GT/s compliance with all jitter elements built in for receiver compliance testing. This includes the new requirement for low and high band random jitter (RJ) as well as the residual spread spectrum clocking signal, represented by a sinusoidal tone.

For transmitter compliance, measurements such as jitter and de-emphasis ratio are also built in. Building on the capabilities of the new PCIe model BERTScope, the Test Bench also includes the BERTScope CRj clock recovery with jitter spectrum analysis for transmitter PLL compliance measurement.

The PCIe Test Bench provides all equipment and accessories needed to make compliance measurements easy. Aimed at design and test engineers who work with chips and add-in cards, the PCIe Test bench includes the PCIe Signal Integrity analyser, the BERTScope CRj option with PCIe PLL analysis capability, PCIe Compliance Baseboard (CBB) version 2, PCIe 2.5GTps transmitter compliance test software, and all cables and adapters for a complete test setup.

The PCIe Test Bench also offers analysis capabilities beyond compliance, allowing fast characterisation of margin and easy troubleshooting, said SyntheSys. Examples include the ability to generate spread spectrum clocking (SSC) to test device performance in real world conditions, and also a unique SSC waveform analysis feature that gives insight into a common area for BER issues.

Delivery of the device is 10 weeks ARO. Upgrade options are available for existing BERTScope customers.

- Gina Roos

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