Program addresses novel IC packaging issues

Two research centers are inviting industry partners to participate in an advanced research program on next-generation flip-chip and substrate technologies. The effort will address key "IC-to-package-to-board" packaging interconnect issues for 32nm ICs and below.

The Microsystems Packaging Research Centre at the Georgia Institute of Technology has teamed with Belgium's IMEC to establish an industrial affiliation program that targets novel packaging approaches designed to reduce the mechanical stress on the IC after packaging and assembly.

Low-stress packaging techniques become indispensable when using copper or low-k on-chip interconnections, particularly since low-k materials typically have very weak mechanical properties.

The program will provide solutions to four major barriers to next-generation flip-chip packaging of scaled ICs and ultra-low-k dielectric ICs: