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Program addresses novel IC packaging issues

Posted: 18 Oct 2007     Print Version  Bookmark and Share

Keywords:flip-chip  substrate technology  packaging interconnect issues  low-k materials 

Two research centers are inviting industry partners to participate in an advanced research program on next-generation flip-chip and substrate technologies. The effort will address key "IC-to-package-to-board" packaging interconnect issues for 32nm ICs and below.

The Microsystems Packaging Research Centre at the Georgia Institute of Technology has teamed with Belgium's IMEC to establish an industrial affiliation program that targets novel packaging approaches designed to reduce the mechanical stress on the IC after packaging and assembly.

Low-stress packaging techniques become indispensable when using copper or low-k on-chip interconnections, particularly since low-k materials typically have very weak mechanical properties.

The program will provide solutions to four major barriers to next-generation flip-chip packaging of scaled ICs and ultra-low-k dielectric ICs:

  • Organic package interposer substrates that minimise stress at the die and package level while enhancing wiring density, fine I/O pitch routing capability and the high-frequency signal performance of substrates.

  • A new generation of fine-pitch, flip-chip under-bump metallisation and barrier metallisation techniques that meet the electromigration and thermo-mechanical reliability targets for flip-chip scaling.

  • Novel solder and non-solder interconnect approaches, including advanced underfill materials and processes to meet future current density, geometry and reliability requirements.

  • Thermo-mechanical modeling, design and verification for improved reliability.

    The two-year program is open to system companies, IC manufacturers and assembly houses.

    The Georgia Tech Centre is a pioneer in package and system integration. IMEC focuses on silicon-centric technologies.

    - Nicolas Mokhoff
    EE Times

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