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EDA/IP  

Xilinx expands functionality of PinAhead tech

Posted: 17 Aug 2007     Print Version  Bookmark and Share

Keywords:software tool  Xilinx FPGA  PCB interface 

Xilinx Inc. has announced the immediate availability of version 9.2 of its PlanAhead hierarchical design and analysis design tool. Promising a full speed grade advantage, this latest release features expanded functionality of Xilinx PinAhead technology. Released earlier this year, PinAhead technology provides FPGA designers with the ability to assign interface I/O groups to I/O pins simply by dragging into a graphical representation of the FPGA.

PlanAhead 9.2 software further simplifies the complexities of managing the interface between the designer's target FPGA and the PCB with the ability to import and export I/O port information through VHDL or Verilog headers.

The new release also offers support for the latest Spartan-3A DSP platform FPGA from Xilinx. With the 9.2 release, PlanAhead software now supports the entire line of Xilinx Spartan-3 generation FPGAs.

"PlanAhead allows designers to divide a larger design up into smaller, more manageable blocks and focus efforts toward optimisation of each module, improving performance and quality of the entire design," said Salil Raje, Xilinx director for Design Planning and Verification. "Our latest 9.2 version allows designers to import and export I/O port information within their native HDL language, which further improves designer productivity."

PlanAhead 9.2 is available on all major OS as an option to the Xilinx ISE design suite. Single-user licenses are currently available at a promotional price of Rs.1.01 lakh ($2,495), US list.




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