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EE Times-India > EDA/IP

Boost productivity with ESL techniques

Posted: 14 Aug 2007     Print Version  Bookmark and Share

Keywords:ESL techniques  HW/SW co-design  RTL implementation flow  SystemC  SystemVerilog 

ESL, which is defined as design and verification done above the RTL, is used today by most semiconductor and system companies. Today, the ESL languages, tools and methodologies that exist fosters reuse and allows the ESL investment to be leveraged across the design process. With ESL, productivity gains from faster system verification, true HW/SW co-development and increased power savings are ready for the taking. With a good understanding of software programming, engineers armed with ESL tools are moving design to the next level of productivity. Read through to know more about ESL.

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