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EE Times-India > EDA/IP

Manufacturability-optimised reconfigurable logic for 65nm, 45nm nodes debuts

Posted: 23 Jul 2007     Print Version  Bookmark and Share

Keywords:reconfigurable logic IP  Moore's Law 

Lightspeed Logic tips a new generation of its Reconfigurable Logic IP for the 65nm and 45nm process nodes. In addition to providing increased flexibility in chip architecture, significant reduction in design cost and rapid time-to-market, the new Manufacturability-Optimised Reconfigurable Logic brings significant benefits to customers designing in advanced geometries. Because of the regularity provided by the tiling structure and the full knowledge of the immediate neighborhood of the tile, Lightspeed Logic, in partnership with its customers, can fully deploy OPC/RET technologies without facing the typical computing limitations associated with standard cell structures. As a result both lithography-related variability and stress-related variability are substantially reduced and the timing modeling does not need to accommodate overly pessimistic guardbanding.

Customers deploying Lightspeed Logic's new Manufacturability-Optimised Logic can isolate the front-end and physical design engineers from the complex post-GDS manipulations and prevent the iterations between manufacturing and design typically experienced in advanced geometries. The Manufacturability-Optimised Logic also enables faster process debug and ramp up and delivers higher yields after the process has been stabilised. The addition of these new capabilities to the already high-density achieved by Lightspeed Logic's Reconfigurable Logic IP will produce a higher number of known-good dies per wafer and effectively outperform the equivalent density of standard cells.

Lightspeed Logic has been collaborating with the industry's leading DFM solutions provider, Clear Shape Technologies to model the manufacturability of the optimised tiles to achieve the goals described above. "Lightspeed Logic's approach, combined with our recognised expertise and manufacturing models validated by the leading IDMs and foundries, is providing our customers with an appealing alternative to master the challenges of 65nm and below," said Atul Sharan, president and CEO of Clear Shape. "Our collaboration brings a unique advantage to designers in addressing nanometer scale semiconductor manufacturing challenges."

"At 65nm and 45nm, Lightspeed Logic's manufacturability optimised reconfigurable logic delivers a yield breakthrough, with yielded die surpassing that of traditional standard cell methodology," said Dave Holt, CEO of Lightspeed Logic. "This combined with increased performance and the increased flexibility in chip architecture, significant reduction in design cost, and rapid time-to-market, are a part of the innovation engine allowing the semiconductor industry to continue to keep pace with Moore's Law".

- Clive Maxfield
Programmable Logic DesignLine

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