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Actel unveils block-based FPGA design

Posted: 20 Jun 2007     Print Version  Bookmark and Share

Keywords:FPGA design tool  FPGA IDE  DSP  flash memory 

Actel Corp. is unveiling SmartDesign, a graphical design entry capability that promises to bring FPGA design to a higher level of abstraction. It's part of Libero IDE v.8.0, the latest version of the IDE for Actel's FPGAs.

Libero IDE serves all of the company's FPGAs, including the flash-based ProASIC3 and the low-power Igloo devices, as well as the Fusion programmable system chip (PSC) mixed-signal power management FPGA. The 8.0 release adds new capabilities for programming flash memory. It's the first Libero release to support Igloo's 5?W capability with 1.2V operation.

SmartDesign lets users graphically create block diagrams from prefabricated blocks from Actel's DirectCore and SmartGen IP libraries, and supports custom blocks written in HDL code. Users can generate synthesisable HDL code and print out the block diagrams for documentation.

"SmartDesign is a block-based design methodology that abstracts your design from the schematic level to the napkin level," said Jake Chuang, director of application solutions marketing at Actel. "Schematic capture exposes you to the full detail of connectivity between different blocks. SmartDesign is one level higher. It only shows you the connectivity relationships between different blocks."

Any given block, he noted, could range "from large IP blocks to small macros." Users can create blocks that range from small partial designs to completed projects. In addition to writing HDL, users can create blocks that represent processor sub-systems created with Actel's CoreConsole tool, or DSPs built with Synplicity's Synplify DSP. "The more you include, the more definite the timing closure or resource usage would be for your block," Chuang said.

While users are building the diagram, a "SmartGuide" feature suggests compatible bus interfaces and IP cores that may be appropriate for the design. This same function serves as a design rule checker, ensuring that connections are correct by construction.Once the block diagram is created, users can generate synthesisable VHDL or Verilog. "One more thing is that you can print directly from it," Chuang said. "We find that customers, especially in the high reliability area, like to have documentation for everything they do. They can save a PDF and file away their high-level design source code."

Meanwhile, a new feature in Actel's FlashPro software, called FlashPoint, lets users modify and edit Flash ROM security settings independently of Libero, making it unnecessary to re-run the design through synthesis, place and route. Now, said Chuang, users can program non-volatile memory from a configurable GUI rather than having to invoke an EDA tool flow.

Libero 8.0 is available now on Windows and Linux platforms for Rs.1.02 lakh ($2,495).

- Richard Goering
EE Times

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