Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Embedded

High-speed DSP cores target 2.5G, 3G base band

Posted: 08 Jun 2007     Print Version  Bookmark and Share

Keywords:DSP cores  2.5G  3G  VoIP  RISC processors 

CEVA Inc. has introduced first three members of its new TeakLite-III family of DSP cores that feature 32bit multipliers to offer the increased precision needed for high-fidelity audio applications and the dual 16x16bit multipliers to boost performance for a wide range of DSP applications.

The TL3210, TL3211 and TL3214 target 2.5G and 3G cellular base band, high definition (HD) audio, VoIP and portable audio players. The TeakLite-III cores are assembly code compatible with previous generation TeakLite cores, but the new cores incorporate many significant enhancements.

Product enhancements
Of particular interest to DSP developers about the new cores is the addition of 32bit and dual 16x16bit multipliers. (The TeakLite I and II have only a single 16bit multiplier.)

The TeakLite-III also gets a speed boost from new audio-oriented instructions and instructions for accelerating FFT, Viterbi and Huffman algorithms. Initial performance estimates by CEVA show TeakLite-III cores to be 4x faster than previous TeakLite cores on basic operations and 2x faster on most popular audio codecs. The new cores will run at 350MHz in a 90nm G process and up to 425MHz in a 65nm G process, under worst case conditions. CEVA said the increase in clock speed is largely enabled by deepening the pipeline to 10 stages, up from 4 stages in previous TeakLite cores. CEVA has also introduced pipelined memory accesses to allow memory to keep pace with the higher clock rates.

More DSP improvements
Other changes include migration to a 32bit architecture (TeakLite I and II were 16bit architectures) and new RISC features. The new RISC features include a 32bit general purpose register bank, a 32bit linear address space that extends the addressable memory to 4GB, a cached memory sub-system that frees the developer from managing memory and branch prediction and conditional instructions, both of which improve the performance of decision-making code.

The TeakLite-III nominally uses 32bit instructions, but it also supports a comprehensive 16bit instruction set dubbed CEVA-Quark. An entire application can be written using only the 16bit Quark instructions, or programmers can mix 16- and 32bit instructions. This allows developers to make trade-offs between code size and performance. (Other instruction sets, such as the ARM Thumb2 instruction set, offer similar capabilities.)

TeakLite III continues the trend in DSP cores of incorporating more control functionality. It will likely compete against other dual-MAC DSPs such as the C55x+, which runs at 400-500MHz under worst case conditions. It will also compete with 32bit RISC processors which incorporate DSP functionality, such as the ARM11 and MIPS24KEc cores.

CEVA reports that two top tier Semiconductor vendors have licensed TeakLite III cores?a U.S.-based vendor developing a multi-mode base band chip and an Asian vendor developing chips for HD audio applications.

CEVA-TL3210 and TL3214 are available for licence today. TL3211 is slated for licensing in early 2008.

- Kenton Williston
DSP DesignLine

Comment on "High-speed DSP cores target 2.5G, 3G..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top