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Package design tool generates Spice-compatible models

Posted: 31 May 2007     Print Version  Bookmark and Share

Keywords:power integrity tool  IC-package co-design solution  Spice modelling 

Apache Design Solutions has announced its Sentinel product line that promises to address system-level power integrity by generating compact Spice-compatible models for easy portability among design teams. This IC-package co-design solution aims to deliver a comprehensive solution for tackling noise and power at the chip, I/O and PCB design levels.

This is the most significant announcement for the company since launching RedHawk over four years ago. It's intended to reach beyond Apache's current market of SoC designers to include I/O and system designers, while utilising the company's power and noise expertise.

Sentinel consists of three integrated components that are automated to work with industry standard tools?Sentinel-CPM for full-chip dynamic power solutions, Sentinel-SSO for high capacity I/O analysis and Sentinel-EMI for noise source modelling for EMI analysis. Sentinel-CPM claims to offer Spice-compatible models with Spice-like accuracy with time savings per run of two to three orders of magnitude.

"Power and cost are the most important design challenges as we move to smaller and smaller geometries, and there is currently no comprehensive solution in the market," said Andrew Yang, Apache Design Solutions CEO. "Power integrity does not stop at the IC level. All noise and power issues are linked together, but key decisions such as package selection and power/pad ratio are made early on in the design process. Without accurate analysis, designers are taking a conservative approach and these decisions may impact the ability of the system to work in the end."

Sentinel-CPM uses a partition-based approach to generate a compact chip power model. The user specifies the number of partitions, 64 or 128, and presses a button. The product will generate a different Spice-compatible model for each location, modelling the spatial and temporal switching characteristics of digital core, memories and IP. It also models on-die power/ground resistance, decoupling capacitance and transistor parasitics. The switching behaviour at each location in the partition is drastically different, so the model generated by Sentinel-CPM claims to provide a very accurate view.

In a comparison run with Apache's RedHawk full chip dynamic simulation, CPU time was 8hrs for a transient simulation of 40 million nodes for 20ns with a 10ps timestep. Using the Spice-compatible models generated by Sentinel-CPM, the 64-partition model contained 128 Vdd/Vss terminals, and the runtime was claimed to be only 12mins with similar accuracy.

Sentinel-SSO provides Spice characterisation for full-bank I/O subsystems for package placement and selection. It models all noise sources and channels that impact the timing and signal integrity. Sentinel-SSO reads a Spice netlist; the user then pushes a button for automated analysis. It links to distributed RLCK and broadband s-parameters.

Apache claims Sentinel-SSO can accurately handle 16 I/Os in less than 1.5hrs of CPU time, so an entire bank of 128 I/Os would take approximately 12hrs. In a test comparison with Spice, Sentinel-SSO tracked almost exactly with the Spice results, the company claims.

Sentinel-EMI is intended to analyse beyond the well-understood conducting noise of signal ports. It also addresses core switching noise and coupling between core and 1/O power domains.

According to Yang, there are no accurate on-chip noise source models that can be linked to EMI, so the analysis has been weak. Even when I/Os are not switching, he noted, they still emanate noise.

Sentinel-CPM is available now, with pricing starting at Rs.42.27 lakh ($100,000). Sentinel-SSO, also starting at Rs.42.27 lakh ($100,000), will begin shipping in Q3 '07. Sentinel-EMI requires Sentinel-CPM and is priced at Rs.21.13 lakh ($50,000). The Sentinel product line is fully integrated for IC-package-board design in a single environment. All three products will be demonstrated in June at the Design Automation Conference.

- Cindi Maciolek
EE Times

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