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Re-synthesis solution offers area, speed, power benefits

Posted: 28 May 2007     Print Version  Bookmark and Share

Keywords:die reduction  digital IC designers  RTL synthesis  IC design libraries 

Nangate Inc. has claimed that its Design optimiser re-synthesis solution will provide digital IC designers with the advantages of full custom design implementation while preserving the benefits of cell-based design methodologies. The EDA start-up said the Design optimiser solution, is capable of creating an optimised gate-level design with area, speed or power benefits.

Built entirely by Nangate, Design optimiser has no licensed or external components in its package and uses patented covering and mapping algorithms developed internally.

Die area reduction
The Design optimiser, due to be available by Q3, has already been put out for evaluation with a select set of customers. An undisclosed beta customer in the communication area said it has been able to gain 24 per cent die area reduction.

"Nangate is now taking a new step, including the synthesis of the transistor layout in itself to become part of the physical synthesis. This brings a much better utilisation of physical synthesis for higher performances, lower costs and lower power consumption," commented Nangate's co-founder, president and CEO Ole Christian Andersen. "The essence of what we are trying to do is to bring together the two disciplines of physical synthesis, on the one hand, and the creation of tailored cell libraries for chip designers, on the other hand."

Andersen explained that all current RTL synthesis tools, offered by Cadence Design Systems, Magma Design Automation and Synopsys, rely on a predefined standard cell library. The libraries are created independently and are re-used for different types of design. The Design optimiser, however, provides the new capability to combine synthesis with library creation for a better utilisation of the CMOS processes. It also enables to identify and uses high pin count and complex gate functions that existing synthesis tools cannot use, he continued.

'Netlist of gates'
"RTL synthesis is basically the process of translating a technology-independent specification in VHDL or Verilog into a netlist of gates from a standard cell library," Andersen further explained. "Design optimiser operates on the gate-level taking as input a gate-level netlist along with a source library, and outputs a new optimised netlist along with a new target library. The target library can be the same as the source library, it can be an augmented library or it can be a completely new library depending on the optimisation mode chosen."

In creating a full library, the library designer must specify what functions are needed and the drive strengths for each function. In addition, the row-height of the cells and the cell template must be specified. These library parameters have a huge impact on how well the RTL synthesis can perform its function. Nangate asserted that Design optimiser combines the optimisation of the library parameters with synthesis and can thereby reach a whole new level of optimisation.

Nangate said Design optimiser is fully compatible with Nangate Library Creator and Library Characteriser. The three solutions are, however, independent, and a company that has a well-established flow can select solely Design optimiser.

- Anne-Francoise Pele
EE Times-Europe

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