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EE Times-India > EDA/IP

T-Spice simulator slashes runtime by 80%

Posted: 26 Apr 2007     Print Version  Bookmark and Share

Keywords:T-Spice simulator multi-core  T-Spice simulator fast runtimes  analogue mixed-signal simulator  SPICE 

Tanner EDA developed T-Spice simulator for analogue and mixed-signal chip designs to be used on computers with multiple processor cores. The simulator enhances design productivity while shortening the design cycle, when integrated with schematic capture and waveform viewing. The device promises 40 per cent faster simulations on single-processor, dual-core computers and 80 per cent faster runtimes on two-processor, dual-core machines.

T-Spice automatically breaks down the workload into small tasks and distributes these tasks to multiple threads for processing. It parallelises the model evaluations during the Newton-Raphson iterations using Intel's Thread Building Blocks (TBB) technology. T-Spice also uses a direct Level-3 BLAS sparse linear solver from Intel for the linear system solution.

The product generates simulations of analogue and mixed-signal IC designs. It can read Hspice and P-Spice netlist formats directly and includes a simulation manager and device modelling features. It offers support for the latest industry models, including Penn State Philips Model (PSP), BSIM3.3, BSIM4.5, BSIM SOI, EKV, MOS11, MOS20, VBIC and MEXTRAM. Proprietary numerical techniques achieve convergence for circuits, which are often impossible to simulate with other SPICE programs and device modelling algorithms allow designers to switch from the fastest table-based model evaluation to the most accurate direct model evaluation. Custom models can be created within T-Spice using algebraic expressions for voltage and current controlled sources, data from external tables or the C programming language.

The device will be available in June. Pricing starts at Rs.2.86 lakh ($6,495).

- Emily Gleason

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