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DDR SDRAM controller using Virtex-4 FPGAs

Posted: 27 Apr 2007     Print Version  Bookmark and Share

Keywords:DDR  SDRAM  Virtex-4  DDR SDRAM  SDRAM controller 

The implementation of a DDR SDRAM controller in a Virtex-4 XC4VLX25 FF668 -10C device requires direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines. This application note explains the reference design for the implementation of these low-cost, high-density DDR SDRAM devices. This reference design has been developed using both SDRAM components and DIMMs.

View the PDF document for more information.

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