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TSMC to start running 55nm prototyping service this May

Posted: 29 Mar 2007     Print Version  Bookmark and Share

Keywords:55nm process technology  manufacturing process  65nm process technology 

Taiwan Semiconductor Manufacturing Co. Ltd will start running its 55nm process technology on a prototype basis in May, initially planning to offer it on a bi-monthly basis.

TSMC said the process is a 90 per cent linear-shrink from its well established 65nm technology, including I/O and analogue circuits, and that it would deliver "significant die cost savings from 65nm, while offering the same speed and 10 to 20 per cent lower power consumption."

In the first phase, the 55nm logic family will be offered in the company's so called "CyberShuttle" programme and include general purpose (GP) and consumer (GC) platforms. Initial production of the 55GP begins in May, followed later in the year by 55GC.

The company says that since the 55nm process is a direct shrink, IP providers can leverage existing libraries and port their 65nm designs with minimal risk and effort.

"TSMC s half node process, including 55nm, is the quickest and simplest way for our customers to be cost competitive in the rapidly changing marketplace," said Jason Chen, vice president of corporate development of TSMC said in a statement early this week (March 27).

Chen said the company has already engaged with leading customers and IP suppliers on the process, and would continue to streamline adoption using its CyberShuttle prototyping programme. This allows multiple customers and IP suppliers to share the costs of a single mask set and prototype wafers on a pilot run.

TSMC first offered its 65nm shuttle service in October 2005. The first shuttle employed two versions of the TSMC 65nm process: the CLN65LP low-power process—which includes low-standard and high-threshold transistors; and the CLN65G general-purpose process.

- John Walko
EE Times Europe

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