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Tool automatically adds clock-gating logic to RTL code

Posted: 28 Mar 2007     Print Version  Bookmark and Share

Keywords:power optimisation  clock gating  PowerPro 

Claiming breakthrough technology in IC power optimisation, Calypto Design Systems Inc. is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code. It uses the company's sequential analysis capability to support clock gating over multiple clock cycles.

PowerPro CG is Calypto's first move from verification into optimisation, but it was planned all along, said Calypto founder and chairman Devadas Varma. "We've been looking at ESL as a means to solve specific problems, and we always thought that would include power optimisation," he said. "We felt that unless we solved the verification problem first, it would be hard to do the design part."

60% less power
PowerPro CG identifies regions of a chip that can be clock-gated to reduce dynamic power. It then automatically generates the clock-gating enable logic, after running a concurrent area, timing and power analysis. Calypto claims PowerPro CG does not hurt area, performance and leakage power. The tool has reduced power by as much as 60 per cent on initial customer designs, the company said.

RTL synthesis tools today provide a clock-gating capability, but that ability is generally restricted to single clock cycles, Varma said. PowerPro CG, he said, can insert clock gating across multiple cycles and across multiple pipeline stages. Compared with synthesis tools, the Calypto product can find more locations for clock gating and can extend the duration of clock gating. The biggest power savings, Varma said, will be for dataflow-intensive designs.

"Synthesis does a combinational analysis within moments of time," said Tom Sandoval, Calypto CEO. "We do a sequential analysis of the circuit over a period of time."

PowerPro CG inserts two types of clock gating, Varma said. One is "observability-based" clock gating, through which the tool finds conditions where the output is stable and propagates backward through a pipeline to find more locations for clock gating. The other is "input stability-based" clock gating. In the latter case, the tool finds conditions where the input is stable and then moves forward in the pipeline to find other locations for clock gating.

Higher clock-gating efficiency
In customer designs, Calypto claims to have measured power savings from 20 per cent to 60 per cent, compared with post-synthesis netlists. In one example, the tool raised clock-gating efficiency from 39 per cent to 62 per cent, the company said.

Inputs to PowerPro CG include synthesisable VHDL or Verilog, Synopsys Design Constraint (SDC) timing information, Switching Activity Interchange Format (SAIF) files and Liberty cell libraries. The output is power-optimised RTL, along with metrics showing the power savings.

Users can set controls for trade-offs with respect to area or performance. They also have a graphical interface that makes it possible to pick and choose which transformations to apply, and to specify "don't touch" areas of the circuit. Alternatively, the tool can run in a fully automated mode. An integrated graphics display provides cross-probing between the schematic and the RTL code in order to show where clock gating is taking place.

There usually aren't any area trade-offs, Varma said, because PowerPro CG only inserts "a small amount of very synthesis-friendly circuitry" to gate the clocks. PowerPro CG is a block-level tool, but there are no technical restrictions on block size, Varma said. The tool is designed for use prior to RTL synthesis.

PowerPro CG is available on Linux platforms starting at Rs.1.30 crore ($295,000). It does not require Slec CG, although that tool can be used to verify the optimisations.

- Richard Goering
EE Times

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