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Audio processors deliver optimised performance, code density

Posted: 27 Mar 2007     Print Version  Bookmark and Share

Keywords:processor  digital audio processor  MCS Logic  SDRAM  SRAM 

MCS Logic has released three digital audio processors that promise optimised performance and code density for the combination of control code and signal processing requirements in digital audio decoding, file system management and system control.

The MLC 3890 integrate programmable ARM7TDMI as system controller and 32bit RISC-DSP processor for MP3/WMA/Ogg decoding and MP3/WMA encoding, and low-power hard-wired CD-ROM decoder. Utilising 0.18µm CMOS technology, MLC 3890 operates at up to 76MHz. The processor also packs 2KB on-chip data SRAM, 32KB on-chip general-purpose data SRAM with 256Mbit SDRAM interface, 32Mbit parallel NVRAM interface and 32Mbit SPI flash interface.

Using 0.13µm CMOS technology, MCS' high-performance processors—MLC 3590 and MLC 3591—operate up to 125MHz. Both devices integrate programmable 32bit ARM946E-S RISC as system controller, 4-way set-associative I-Cache/D-Cache, MP3/WMA/Ogg/ACC-LC/ACC decoding and MP3/WMA encoding, and low-power dedicated hard-wired CD-ROM decoder.

Targeting portable digital flash/HDD/CD audio products, MLC 3590 and MLC 3591 offer 16KB TCM memory and 64KB general-purpose SRAM with 256Mbit SDRAM and 32Mbit parallel NVRAM interface. MLC 3591 has 64Mbit SRAM on-chip. The processors also feature 79 GPIOs, extra external interface function, 29 programmable interrupt sources and CD-ROM decoder.

The MLC 3890 is packed in 144 LQFP/FBGA and 128 TQFP, while MLC 3590 is in 208-FBGA-1212 and MLC 3591 in 272-FBGA-1515.

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