Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > T&M

Address SI issues in high-speed board design

Posted: 16 Mar 2007     Print Version  Bookmark and Share

Keywords:signal integrity  SI  ASIC  flip chip packaging  processors 

This article discusses some of the SI challenges and the factors associated with high-speed interface designs that are enabled with key features of a RapidIO switch.

View the PDF document for more information.

Comment on "Address SI issues in high-speed boar..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top