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EE Times-India > EDA/IP

Verification box exceeds 200MHz speeds, ASIC gates

Posted: 01 Feb 2007     Print Version  Bookmark and Share

Keywords:verification  prototyping  FPGA  Gidel  Altera 

Claiming breakthroughs in speed, price, capacity and interconnect flexibility for hardware-assisted verification, Gidel Ltd this week is rolling out its Proc_SoC rapid prototyping system.

The Proc_SoC claims to exceed verification speeds of 200MHz, thanks to a direct FPGA-to-FPGA interconnect scheme. It also claims to scale up to 10 crore ASIC gates. Until now, Gidel has been a provider of board-level products. The new system is Gidel's first "box," said Ralph Zak, Gidel's director of North American sales.

The Proc_SoC includes a card cage with up to ten reconfigurable Proc3M elements. Each of these elements has two interconnected Altera Stratix II EP2S180 FPGAs and 128MB of DRAM, with a capacity of 30 lakh gates per element. Ten elements yields three crore gates in one Proc30M module, and Gidel claims the system is scalable up to 10 crore ASIC gates.

Unique interconnect
What's really unique about the system, Zak said, is the interconnect. Other prototyping systems and emulators, he said, require intermediate routing through switching chips or backplanes. "Our goal was to try to provide massive amounts of interconnect that users can define without needing to route through other FPGAs or programmable backplanes," he said.

The Proc_SoC, he said, allows direct connections from any FPGA to any FPGA. There are six connectors for each FPGA, and to connect to another, Zak said, the user has only to run a short 118-pin cable between them.

Development tools
The Proc_SoC comes with the Proc Developer's Kit. It includes tools for mapping chip designs into the FPGAs, and for debugging designs. The kit leverages the Altera Quartus II software for FPGA synthesis, placement and routing. The kit also includes the Proc_Wizard software for configuring and debugging ASIC designs.

Gidel also provides Proc_HILs, a utility that allows a connection to The Mathwork's Simulink environment. It works with the Altera DSP Builder, Synplicity Synplify DSP, or The Mathworks' HDL Coder to map Simulink models into RTL code for the Proc_SoC system. It replaces the Simulink models with the RTL code, while allowing the user to remain in the Simulink environment in order to run tests.

Prices start around Rs.45.32 lakh ($100,000), and a three crore gate system is around Rs.1.36 crore ($300,000). The system will ship this quarter.

- Richard Goering

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