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PCIe 2.0 spec doubles transfer rate

Posted: 18 Jan 2007     Print Version  Bookmark and Share

Keywords:PCI-SIG  PCIe  PCIe 2.0 

PCI-SIG, the Special Interest Group responsible for the PCIe standard, has released the PCIe base 2.0 specification, which doubles the interconnect bit rate from 2.5GTp to 5GTps to support high-bandwidth applications.

The specification extends data rate to 5GTps, while remaining compatible with all existing PCIe 1.1 products that support 2.5GTps signalling. Faster signalling is the key benefit of the new specification, which increases the aggregate bandwidth of a 16-lane link to approximately 16GBps. This higher bandwidth can allow implementation of narrower interconnect links to increase performance and lower cost.

"In today's world, applications are becoming more advanced and are requiring more bandwidth," said Al Yanes, PCI-SIG chairman and president. "This is the perfect time to release PCIe 2.0, which not only supports high-bandwidth applications such as high-end graphics, but also adds many new architectural enhancements."

Aside from faster signalling rate, the PCIe base 2.0 specification also includes several new protocol layer improvements which can allow developers to design more intelligent devices and to optimise platform performance and power consumption while maintaining interoperability, low cost and fast market introduction.

Architecture improvements include dynamic link speed management, which allows developers to control the speed at which the link is operating; link bandwidth notification, which alerts platform software of changes in link speed and width; capability structure expansion, which increases control registers to better manage devices, slots and the interconnect; access control services, which allows for optional controls to manage peer-to-peer transactions; completion timeout control, which allows developers to define a required disable mechanism for transaction timeouts; function-level reset, which provides an optional mechanism to reset functions within a multi-function device; and power limit redefinition, which enables slot power limit values to accommodate devices that consume higher power.

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