Global Sources
EE Times-India
EE Times-India > EDA/IP

Power efficiency impacts chip design

Posted: 11 Jan 2007     Print Version  Bookmark and Share

Keywords:chip design  power consumption  VLSI Conference 2007  Mark Horowitz  semiconductor 

A compelling force that affects chip design today, power consumption is the primary limiter of a chip's performance. The need to create power-efficient designs is having a fundamental impact on IC design.

Prof. Mark Horowitz presented his research findings on this topic, in the plenary session of the VLSI Conference 2007, on Monday (Jan. 8). Horowitz is professor and director of the computer systems lab, Stanford University, and Rambus Inc.

In the mid-1980s, the growth in power consumption that accompanied the upward scaling of chips, forced the semiconductor industry to focus on CMOS technology, and address nMOS and bipolars at niche applications. However, 20 years later, CMOS technology is facing power issues of its own.

"Previously, the power consumed by a function (for instance, a processor) shrunk in relationship with the size. So, if you filled up the same die area, the power would remain roughly the same," Prof. Mark Horowitz pointed out to EE Times India shortly after his talk. "However, today, if you fill up the die again the same way, it will consume more power, as the total power is not shrinking as fast as the size."

New design approaches will have to look at the problem, from a performance efficiency perspective. The goal of design is, to maximise the performance, for a given amount of power.

"Designers used to be focused on high performance systems, previously. Now, they have to worry about not just what the performance is, but what is the energy cost of getting that performance. They have to choose solutions that have very good power efficiency," Horowitz explained.

Although there may be many possible directions that one can look at for achieving power efficiency, he indicated that the approach to energy efficiency will probably take the form of some level of domain optimisation. "What the right solution is for wireless, or signal processing in the front-end of a wireless system, might be different from that for the graphics or the user interface. I think we will see some domain specialisation," Horowitz noted.

Designing power efficient chips will require the designer to be efficient at all levels. "If you do something at the architectural level, you will actually have to know the implementation implications, to know how good the architecture is. I think there will be a lot of coupling between these."

Designers will also have to maintain a relationship between leakage power and dynamic power. "Lower leakage energy will degrade your performance. Hence, to acquire the same performance, you have to increase your power supply, which will increase in turn your dynamic power," he said. "People have demonstrated that in optimal designs, the leakage energy should be about 40 to 50 per cent of the dynamic power."

In future, with functions are shrinking faster than the power consumption, finding an approach to decrease the average power of a gate will be an imperative for designers.

"You could do that either by slowing down the gate, or by running only one or a few of the many blocks on a chips. That would mean that most of the gates are not going to be running all of the time," Horowitz concluded. This would have a strong ramification for the underlying device as well as system design.

- Krishnan Sivaramakrishnan
  EE Times India

Comment on "Power efficiency impacts chip design"
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top