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Cadence incisive formal verifier selected for Ubicom's logic design team

Posted: 08 Jan 2007     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  Ubicom  Incisive Formal Verifier  networking processors 

Cadence Design Systems Inc. has announced that Ubicom, a developer in communications and media processor (CMP) and software platforms, has incorporated the Cadence Incisive Formal Verifier solution into its overall design flow. This has allowed Ubicom to streamline the overall time needed to verify some of their most advanced products that drive interactive applications and multimedia content for the digital home.

The Incisive Formal Verifier solution was selected by Ubicom due to a combination of factors including performance and capacity, ease of use, comprehensive methodology, ease of flow integration, ease of adoption, and support infrastructure. Formal Verifier technology enabled Ubicom to identify bugs that had eluded simulation-based verification. With assistance from Cadence, Ubicom quickly built up a strong foundation and a much improved process for design team verification, including integration of best-practices related to deployment and proliferation of an assertion-based verification flow.

Ubicom plans to be up and running formal assertion verification weeks or even months prior to simulation on some of their most advanced and unique multithreaded networking processors.

Part of the Cadence Logic Design Team Solution, "Design with Verification," Incisive Formal Verifier technology provides an efficient way to perform early verification, and provides usability synergies with the Incisive Design Team Simulator. The formal technology exposes most functional bugs early in the development of the design, including complex corner-case bugs, protocol compliance issues, and verification of problem-prone areas, significantly reducing quality risks.

The software also goes one step further by validating and offering proper design fixes for users. This enables designers and verification engineers to verify individual blocks months prior to test bench simulation, and to complement traditional verification techniques. The solution also speeds up design integration and validation efforts, adding further to faster turn-around and an overall productivity boost for engineering teams.




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