Global Sources
EE Times-India
EE Times-India > EDA/IP

Cadence CEO discusses emerging trends in semicon design

Posted: 06 Dec 2006     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  Michael J. Fister  CDN Live India 2006  semiconductor design  IC design 

Fister: India is a very fun place to come to because Cadence is often a component of these companies' plans. It is one of the reasons why we want to be local to the customers here, and why we put our R&D people here.

Michael J. Fister, president and chief executive officer, Cadence Design Systems Inc. interacted live with EE Times India's Mumbai-based Bureau Chief, Krishnan Sivaramakrishnan, following his keynote address at Cadence's CDN Live India 2006 event held at Bangalore in mid-October. Fister discussed how Cadence is responding to some of the emerging trends in the semiconductor design sector—particularly, the growing complexity of IC design, the critical requirement to minimise power consumption, and manufacturability of complex IC designs—that are together defining how EDA tools will evolve in the future.

The core of Fister's view is that, as design complexity across custom ICs, digital ICs, PCB and packaging increases, a holistic level of capabilities are now required from semiconductor design and EDA companies alike. He defines the holistic approach as a systematic approach to being more intelligent about the whole design process.

Coming to Cadence from a 17-year stint at Intel Corp., the very first thing Fister did in Cadence was to drive this holistic concept 'into the fabric' of the company. Fister also explained how semiconductor design, in response to the increasing design complexity, challenging time-to-market requirement, and high investment levels, is shifting from SoC to system-in-package, and platform based development; and how EDA technology and products are supporting and facilitating these design approaches.

Prior to joining Cadence, Fister was Intel's senior vice president and general manager of Intel's Enterprise Platforms Group, which designs, markets, and supports building blocks for enterprise computing.

A graduate of the University of Cincinnati, Fister received a MS in electrical engineering in 1978. He then worked in executive and engineering management positions at Wyse, Machine Vision International and Cincinnati Milacron. He is currently on the board of directors of Autodesk Corp. and two non-profit organisations, the National Action Council for Minorities in Engineering (NACME) and the Leukemia & Lymphoma Society

EE Times India: The increasing complexity of IC designs trends is having a deep impact on the development of EDA tools. How is Cadence responding to this?
: As design complexity across the custom, digital, PCB and packaging increases, a holistic level of capabilities is required. I come from an IT industry background, where we applied technology to allow the industry to innovate at a higher level of abstraction.

The very first thing that I did in Cadence is, drive this holistic concept into the fabric of the company. And, what that amounted to was getting our pockets of experts, who are working on the digital part of the tool chain, the analogue part of the tool chain or the mixed signal part to work together. This also allowed us to optimise between our tools, as opposed to just integrate them. Our customers were accustomed to buying a point tool from us or from a competitor or even innovated a block themselves. That way, they never could take advantage of these tools working together. When we go to our customers today, they can see the totality of what we are doing. So that alone has been a breakthrough.

I think this is very well manifested in the Virtuoso platform. From the specification right through to manufacturing, things come together with a uniform human interface. When we allow these to be seamless, we can implement concepts like constraints—we can specify that we want two elements to be linked and the system of constraints automatically tracks it all the way through the process, so we cannot break it.

And this leads us to the second thing. We can then project where we go up the abstraction, into verification as a process, system level design, software level design and manufacturability.

EE Times India: In your keynote address at CDN Live India 2006, you talked about the pervasiveness of architecture, and how architecture is entering the domain of manufacturing. What are the key elements of this architectural approach?
: I hope people see the architectural approach as a way to do things right the first time. You hear euphemisms in the industry such as 'correct by construction' and 'designed for manufacturability'. The whole notions are the same.

One key element of that architectural approach is a systematic approach to being more intelligent about the whole design process. The second aspect is that you cannot rely on incremental things—multi-threshold transistors, and islands of voltage automation—to help facilitate some amount of power minimisation. I believe passionately that we can look at the problem seamlessly, from end to end. For instance, you can cache your power intent and keep it through the continuum to get even bigger impact.

EE Times India: How do you view the challenges posed by the DFM requirement?
: I have an example from history—in the design of dynamic memories, error checking and correction, a combination of design and manufacturing, was a boon to the manufacturability. It is an architectural approach, which can algorithmically detect and correct any single bit error either in the word or the check bits. And, you can detect a double bit error. So, you never even accidentally make a mistake.

In today's world, that manufacturability parses into aspects like power, for some users, power is important—a higher power chip is worse than a lower power chip, if you want to run on a battery. To others, a faster chip is better than a slower chip such as in a microprocessor. It is a very disperse space.

To be able to address this is very dependent on a company having a lot of technological curiosity. You have to deal with lithographic effect, chemical etch effect, the effect of getting hills and mountains as we deposit metal.

Some prominent industry watchers are making amazing statements about how no big company will ever address this effectively. Well, I think no small company can come up with that, because you have to reach up into the design continuum to do it right at conception. You are not going to do it as a post-process check.

Our approach is to consider a particular piece of technology or application and work with our customers, as it is a disperse space. And, as we share insights with customers, we can actually demonstrate the linkage of design and manufacturability.

We are very much engaged with our technology partners in the ecosystem—equipment manufactures, foundries inside and outside the companies, and our customers, trying to help them solve their manufacturability problems.

EE Times India: You also mentioned that design, in response to the increasing complexity, has moved from SoCs on to SIPs, and platform based development. Can you sketch that evolution?
And, could you also provide a brief idea of Cadence's work in this area?
: The architectural approach can apply, regardless of how the integration is done. If you think about it all the way back to a computer system design, we used a printed circuit board, and then we made ICs, and with more passes of ICs, we built a system. That is where the notion of the system comes.

Many integrations on die were just miniaturisations of that. What you realise is that you might as well use some of the blocks as they already exist. To give you an example, people built billions of memory chips—some of these are non-volatile, and some are dynamic. To put these on a die is a mixture of process—you are trying to get the same kind of density requirements; some of the characteristics to connect these are very complex. So, if you have a time to market panic on your hands, why not build them on a system in a package.

The approach works very well for things like memories, and analogue components, some or many of which are manufactured on a quarter micron. This is because the power or the voltage they are going to operate on, do not miniaturise very well.

Customers can then concentrate on the main functionality. They can re-use pieces that already exist and innovate in the space they want to; and at the minimum, enter markets quicker. This is mostly the purview of big companies now. We are working with companies like STMicroelectronics, and also very closely with a consumer electronics company.

There is also an example of a company's mixed signal integration. Many times, these are the protagonists for an eventual system on chip on dye integration, as there is always a cost advantage in being able to carry out the big silicon integration.

Conserving the platform design or architectural approach to this end idea, is a fine example of the breadth of Cadence's capabilities. We are taking our technology prowess in verification, packaging, analogue, digital and mixed signal all the way to manufacturing. We have put together a kit of components that includes tools, best practises, and integration of blocks of IP from our customers and the rest of the ecosystem. We can now apply these on vertical domains like wireless, personal entertainment, or in future, even automotive.

We are in a very sound position with our simulation and emulation technologies. It is a very nice growth dynamic for the company. We do some of that innovation in India, in our NOIDA design centre. There are some very progressive companies such as ST, TI and Freescale, which are involved in the process.

EE Times India: What are the areas that the recently announced Virtuoso platform addresses?
What is the thought process behind the development of that platform?
: Virtuoso is a custom IC platform that addresses full custom, analogue, RF, RF coming into microwave, and memory. There is a lot of commonality in these areas, at a micro level. Most of those are pervasive elements of mixed signal. So, it becomes a surrogate for mixed signal, and it is also a surrogate for a high performance digital, most of our customers might see it that way.

What makes it more relevant is that, as you move digital devices down the physics of miniaturisation, there are significant analogue effects that you have to deal with, such as transmission effects and other reliability effects. Traditionally, most of these problems are handled reactively, often triggered by a customer feedback. In contrast, the holistic view tries to anticipate these issues, and the Virtuoso platform is an excellent framework that is able to consider the specification and its manufacturing effects.

To give you a further sense of the level of complexity that can only be handled by automation, there are multi variable problems where we have to think about five things simultaneously. For the EDA industry, there is a mathematical foundation for all this; at a fundamental level, most of our people are mathematicians, numerical analysts or algorithm developers. And, the technology that they are developing is focusing on moving the problems up the abstraction level, into the domain of architectural exploration.

EE Times India: Could you elaborate on the nature of the multi variable problems that you referred to?
: The simplest way to think of it is an example of the convergence of multi element optimisation. If you think back 10 years, we were mostly concentrated on the physical area of a chip, where we were trying to make the chips smaller and smaller. Then, we tried to make fast chips as well as small chips, so frequency became important.

Today, we have area, frequency and power. If you build a fast chip and it consumes or dissipates a lot of power, and your phone handset only lasts for five minutes then that is not too good. This is the multi element optimisation which looks at the problem in a three dimensional universe and tries to converge on the best based approximation.

Now, guess what? We have to deal with area, frequency, power, elements of manufacturability, elements of yield and elements of lithography. To us, all this is a mathematics problem at a core technology level. In future, this is not going to be limited to a five dimensional problem, its going to be a 25-dimensional problem.

EE Times India: Will this approach of a framework that you described, be embodied in Torino? To put it another way, will all your EDA platforms have a single unified approach to the design problem?
: Currently, we have segmented digital design capability in our products—L, XL and GXL that address from low end to high end, along the scale of complexity.

We felt the need for a feeder to supply the next generation better. Torino is a feeder technology that brings together the next generation ideas, into a broader framework.

Our current digital platform, like Virtuoso, is already a very complete platform. It integrates place-and-route, which some would consider as a back-end process; and front-end synthesis, which some would consider as a front-end activity; and it integrates elements of verification and manufacturability, as you go up the L, XL and GXL.

Torino extends that sophistication to include recursion. So, if you are thinking and exploring an idea at one end, you can consider it even more seamlessly down into the other end of the problem. This recursion is now handled as a human process. Torino just takes the human processes, and makes these more seamless.

EE Times India: Will it also incorporate design approaches like programmability?
: Implicitly yes, because the specification a lot of which are explored architecturally, is a trade off between what is implemented in big blocks—should it have two ARM cores or not?
If I have multiple cores, how do I have bus interconnects?
If I am doing that then I am essentially having programmability. Co-design of the software and hardware elements does not want to be left till the end.

With our current verification schemes, which include simulation and emulation, we actually have people using the co-design technique to develop software, while the chip is being developed. That has a logical piece in the simulation in the architectural development. Also, you can see the time to market impact because you parallelize the activity. That is just the tip of the iceberg in what we are doing there.

If you are trying to solve the problem of time to market and productivity, a large element of that is, it is very expensive if you have to do things over again. Things are not any more about putting elements into a chip. Now, you got the chip, you have to put the chip into something, and then it becomes all about ramping that.

Whether it is your iPod, voice recorder, or phone handset, this is a tremendous concern. The innovation comes not just from a hardware person, software person or manufacturing. It is also the people writing the applications on top of these, and the mechanical enclosures that it is going into. The whole thing is about trying to build that phone or iPod and ramp it up fast, because it is going to become obsolete soon.

Platform design complements the idea of moving up the abstraction, and it continues to engulf a larger number of people, who have to do co-design with the sub-components in here. That is why we call it system—system design, system on a chip, system in a package.

EE Times India: Do you see a force to move to open standards becoming more compelling for economic reasons?
: I don't know; that's a good question. We are certainly trying to use the standards industry as a way of rallying our industry partners and customers.

I suppose a cynic can look at some of the past efforts of the EDA industry, and ask us, why do you want to deal with it? However, most of those examples have largely been multiple or redundant implementations of something.

With the Power Forward Initiative (PFI), we will show how we are walking the talk—we have done that with Open Access and we will do that with Power Forward.

We will take a lot of good ideas, and get a core of people to work together. And, once we quickly settle on what we are going to do, we will invite a larger core of people. That is the way we have driven the Power Forward.

Power Forward is based on very sound technology. It is a wonderful example of us trying to use the standards industry as a rallying point for that. We will show just how thoughtful and methodical that process is.

We have established a concentrated ecosystem that includes customers and partners. I hope that ultimately it will all converge, and if it does not then it will not be our fault—it will be some other element of the history of the industry repeating itself.

We are going to try that as a great demonstrable, because power is such a big issue, and is so pervasive across many contexts. We will use our experience to colour how aggressively we drive for standardisation or we just work with the piece of the ecosystem ourselves.

EE Times India: What stage is the PFI in?
: We have it in the Si2, which is active and now promoting it. And, we have just completed a meeting of the core partners. We will have the next round of opening up the PFI further, in the next few weeks. We have already approached the IEEE for the working group, which I think will happen in December 2006.

We will expose more and more of what we have as the fundamental technology, for collaboration and contribution, with the ever growing circle of people for PFI. In the past month, two more companies have joined the circle. We have very enthusiastic responses from people, who have been exposed to it, to the totality of what we are trying to do. There is a lot of technological foundation for what we are doing, and hence it is making progress.

EE Times India: Some of the business challenges for EDA are a price pressure on tools, with end customers facing cost pressures; and EDA companies not able to realise a higher share of the value that gets created in the design system?
How do you deal with that?
: We plan to garner value by demonstrating value. If we ask our customers—as we demonstrate more value, can we expect to earn more value from you? I think our customers will universally say yes.

Our holistic approach is one element of both showing the roadmap that we are on, and allowing us to project that roadmap and garner value. The second is to stratify the more mature elements of our products into a segmented capability. The best example is the stratification of L, XL and GXL.

For many customers doing a category of the chips, they do not need all the facilities of the most glamorous technology. So, we sell them the L version, at a more competitive price. In EDA, if only a part of the technology we sell is utilised, all the discussion the customer has with us is about relating the price to the level of usage of the technology.

With our holistic approach and our ability to stratify elements into a segmented product offering, we will try to demonstrate much more package-able value, and allow our customers to retrieve higher value as time goes on.

EE Times India: Do you find the rate of growth of EDA industry low?
What do you see as the growth drivers in the future?
: It is certainly a challenge. The total market has not grown appreciably for the past five years.

In 2005, it grew by one or two per cent. I think most of that was a consequence of our growth, as we grew faster than the total industry. We had forecast a seven per cent top line growth, and we grew at 11 per cent. And, in 2006, the EDA consortium has just issued its analysis for the past quarter—and it is always one quarter lagging, and it is much better growth. Our first two quarters exhibited growth faster than what we had predicted.

I think this is perhaps an indication of how the holistic view and the technologies we offer are more valuable, especially in the verification space. In probably some more time, we will see the impact of the technology on the manufacturability space, which has a slightly longer gestation period.

We will be able to demonstrate total industry growth, only by showing how our customers can continue to innovate using the tools. As we move up in the verification space, we are addressing a larger pool of people then just silicon designers; we are tapping into a pool of system designers, and software engineers, who are involved in either architectural exploration and verification or co-design. I am optimistic about this as a growth dynamic for Cadence.

EE Times India: How do you view the opportunity in India?
: You have big companies coming here in India. Often they will try fresh ideas, in a kind of a greenfield orientation. For instance, they will take a part of their design flow, and try something different with that. It is not just about rebuilding something they already have—it is trying a much bigger piece with it.

For me, India is a very fun place to come to, because Cadence is often a component of these companies' plans. It is one of the reasons why we want to be local to the customers here, and we have also put our R&D people here. It is a very key component of a fast learning back into our system. It is a great microcosm.

I think the most interesting thing I can see in this visit after six months is the increase in the ability of companies here to not only locally consume products but also specify products. It is very exciting as that specification can nicely raise the level of abstraction.

- Krishnan Sivaramakrishnan
EE Times India

Comment on "Cadence CEO discusses emerging trend..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top