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EE Times-India > EDA/IP

Clear Shape debuts as DFM solutions provider

Posted: 29 Nov 2006     Print Version  Bookmark and Share

Keywords:Clear Shape Technologies  DFM solutions provider 

Clear Shape Technologies Inc. has introduced itself as a DFM solutions provider delivering variability solutions that enable chip designers to control and optimise the parametric and catastrophic impact of systematic manufacturing variations. After three years of development of key patent-pending technologies and successful joint work with several customers and foundries, Clear Shape also announced today two products that enable designers and manufacturers to achieve entitled performance and yield.

Clear Shape has raised Rs.45.52 crore ($10 million) of funding to date, from premiere firms such as USVP, Intel Capital, KT Ventures (KLA-Tencor) and AsiaTech. The company's board of outside directors includes Winston S. Fu, Ph.D., General Partner, US Venture Partners, and Professor Thomas Kailath, Hitachi America Professor of Engineering, Emeritus, Stanford University.

"The foundation that was the basis for the contract between IC design and manufacturing has been shaken as 'rule-based' assumptions have steadily crumbled. Manufacturing variations now dramatically and adversely impact chip performance and yield. There is a dire need for tools and technologies that reinstate designers' confidence that their chips will achieve entitled performance and be manufacturable at high yields," stated Atul Sharan, President and CEO of Clear Shape. "For three years now, Clear Shape has been focused on building innovative model-based solutions from the ground up resulting in its Variability Platform."

At 90nm and below, systematic variations are the greatest cause of catastrophic chip failures and electrical issues related to timing, signal integrity and leakage power. For example, at 65nm, systematic variations of 3nm on a transistor gate can cause a 20 per cent variation in delay and have a 2x impact on leakage power.

Up to 90nm, the industry addressed 'yield' issues with post-tape-out compute-intensive OPC and RET techniques without designers getting involved. This landscape changes at sub-90nm when systematic variations affect both designers and manufacturers. These pattern-dependent systematic variations due to lithography, CMP etc. cannot be accounted for using traditional rule-based tools and methodologies.

With the current corner-based design methodologies and tools, margins are applied everywhere regardless of context. This over-design with excessive guard-banding can result in chip performance that is dramatically lower than entitled performance, also resulting in unexpected parametric and catastrophic failures.

To address these fundamental limitations of the current design infrastructure, Clear Shape has developed a variability platform based on its innovative model-based solution that incorporates process information related to lithography, RET, OPC, CMP, mask, etch, and transistor modelling. Instead of working from layout and approximating the systematic variations effects through excessive rules and margins, designers can now implement, verify and optimise their design based on true silicon shapes, quickly and accurately detect potential manufacturing failures during physical design and use Clear Shape's in-context model-based electrical DFM to optimise their electrical parameters within their existing rule-based design tools.

Clear Shape's goal is to enable designers to achieve entitled performance and yield by providing tools and technologies that fit non-disruptively into existing design flows.

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