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Revised VHDL spec boosts IP security

Posted: 16 Nov 2006     Print Version  Bookmark and Share

Keywords:Accelera  VHDL  Verilog  design language  IEEE 

The Accellera standards organisation has approved a revised version of the VHDL specification, marking a huge step forward for the design language. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for intellectual property (IP) encryption.

Though VHDL had heavy backing from EDA vendors when it emerged as a standard in the late 1980s, most U.S. chip designers stayed with Verilog. According to Gary Smith, chief EDA analyst at Gartner Dataquest, VHDL usage today is declining for high-end design. He adds that the language, however, remains in use at some companies in Europe and Japan, and FPGA designers continue to employ it.

VHDL has been part of the IEEE standards process for many years, and the most recent revision is IEEE 1076-2002. But the IEEE VHDL Analysis and Standardisation Group failed to make much progress with the language after 2002, according to Accellera chairman Shrenik Mehta. Thus, in September 2005, it turned to Accellera for help. Accellera's VHDL technical subcommittee got to work, with support from such companies as Nokia, Rockwell, IBM, Cadence Design Systems, Mentor Graphics and Synopsys.

The first part of the Accellera work, the VHDL Programming Interface (VHPI), was delivered to IEEE earlier this year. Accellera now introduces the second part, internally called Accellera VHDL-2006 3.0.

The integration of PSL is among the most important enhancements in the VHDL revision. PSL statements can now appear within VHDL, where PSL has its own object class. Alternatively, users can create PSL "design units" that separate the PSL assertions from the rest of the VHDL code, said Lance Thompson, chairman of the Accellera VHDL technical subcommittee and senior engineer for IBM's technology collaboration solutions group.

Huge addition
IP protection is a "huge" addition to VHDL, Thompson pointed out. "If you have a significant investment in IP, you don't want to give out source code that enables users to do whatever they want with it. On the other hand, you want to facilitate its use in simulation, so users can correctly interface to the IP."

Thompson said the VHDL committee adapted an encryption approach that Cadence had developed for Verilog, adding "a mechanism for hiding pieces of the source code and encrypting it with different methods." Tool suppliers can decrypt the code so it remains hidden from the IP user. The encryption is accomplished with pragmas that indicate the area of code that needs to be encrypted. Users can specify which encryption algorithm and key to use. A "viewpoints" feature lets users see signal values during simulation, but not how those values are derived.

Another feature is the addition of fixed- and floating-point packages with generics for customisation. Thompson said the move responds to "a long effort on the sidelines to develop synthesisable fixed- and floating-point packages for people who develop DSPs."

Accellera VHDL-2006 3.0 also adds a "process (all)" construct, which provides simplified sensitivity lists. That's a big help in maintaining equivalence between synthesis and simulation, so that VHDL processes aren't synthesised one way and simulated another, Thompson said.

Other enhancements include parameterizable packages using generics; hierarchical signal references for testbenches; composite types that permit elements to be unconstrained arrays; simplified conditionals; unary reduction operators; overloading of logic operators; and some 50 corrections and clarifications to the previous revision of the language.

The revised VHDL standard is available to Accellera members at has Accellera's recommended improvements, Thompson said, but Accellera is recommending a period of trial implementation by vendors before IEEE completes standardisation.

Meanwhile, Accellera is "starting to work on object-oriented aspects for VHDL, largely as an underpinning to support transaction-level modelling," Thompson said. "It looks like we'll be able to use the underlying mechanism to support interfaces for design units and constrained-random simulation environments. And we're open to ideas."

- Richard Goering
EE Times

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