Global Sources
EE Times-India
EE Times-India > EDA/IP

FMA announces environment for ASIC, COT customers

Posted: 25 Jul 2006     Print Version  Bookmark and Share

Keywords:Fujitsu Microelectronics America  FMA  statistical timing analysis  Anova Solutions 

Fujitsu Microelectronics America Inc. (FMA) announced that it is the first semiconductor supplier to provide a comprehensive environment for statistical timing analysis for ASIC and COT customers. According to FMA, the new environment enables designers to reduce the design-optimisation time in layout designs by allowing them to calculate the circuit delays using statistical analysis of the impact of process variations.

Statistical timing-analysis techniques, which check if a circuit can function at a targeted frequency, are becoming a key design for manufacturing requirement for resolving the challenges of the fabrication process during the design phase. The environment provided by Fujitsu can handle the delay variations of transistors statistically, which enables layout designers to estimate the circuit delay more accurately and optimise the circuit effectively so that it can run at the targeted frequency. As a result, timing optimisation turn-around time can be reduced by up to 30 per cent, the company said.

The environment includes statistical static-timing-analysis tools developed together by Fujitsu Ltd, Fujitsu VLSI Ltd and Fujitsu Laboratories Ltd, and cell libraries with process variations. The Anova Suite, developed by Anova Solutions Inc., has been implemented in the environment in order to analyse process variations and characterize library cells.

"The ability to analyse the impact of process variations in deep-submicron technologies at the cell design stage is a significant breakthrough for ASIC and COT designers," said Yoshio Kuniyasu, senior director of SoC design engineering centre for FMA. "Fujitsu has teamed with Anova to provide a comprehensive environment developed to resolve this challenge. We are confident that our customers will realise significant reductions in timing optimisation turn-around time as they implement the system."

Comment on "FMA announces environment for ASIC, ..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top