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Sequence Design to demo clock power analysis at DAC

Posted: 21 Jul 2006     Print Version  Bookmark and Share

Keywords:Sequence Design  Design Automation Conference  Clock Power Analysis 

At next week's Design Automation Conference (DAC) in San Francisco, customers will be introduced to Sequence Design's Clock Power Analysis and Voltage Island Analysis options for its low-power physical analysis and optimisation tools, CoolTime and CoolPower. Sequence's PowerTheater-65 already manages and analyzes these silicon-aware effects at RTL.

According to Sequence Design, the Clock Power Analysis option enables significant reductions in clock network power, often the biggest component of dynamic power. Voltage Island Analysis lets users easily and quickly optimise islands, speeding design time and accuracy, the company added.

"The tribe has spoken, and they are demanding these huge additions to the Cool Products low-power design portfolio," said Sequence president and CEO Vic Kulkarni. "We are leaving the competition in the dust with greatly improved performance paired with unequalled user friendliness."

CoolTime and CoolPower are both concurrent and SI-aware, providing fast design closure times by preventing time-consuming iterations between separate timing, SI and power analysis, and optimisation tools. CoolTime benchmarks consistently demonstrate its ability to scalp its nearest competitor.

CoolPower contains the industry's richest set of power optimisation capabilities. Both dynamic and leakage power can be automatically optimized using CoolPower's cell resizing and Multi-Vt cell swapping features respectively, and MTCMOS power gating analysis offers the most effective method of reducing leakage power by 10x to 100x or more.

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