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EE Times-India > EDA/IP

Sequence, Bluespec offer ESL design for performance, area, power

Posted: 10 Jul 2006     Print Version  Bookmark and Share

Keywords:Sequence Design  Bluespec Inc.  ESL  tool market 

Offering users ESL productivity combined with an ability to analyze various architectures for performance, area and power is the goal of the collaborative effort between Sequence Design and Bluespec Inc.

"Performance, area and power are the three competitive technology parameters for SoC design," said Bluespec CEO, Shiv Tasker. "Sequence's PowerTheater power management solution and Bluespec's ESL synthesis technology combine perfectly to optimize all of these critical variables."

Bluespec's ESL Synthesis automatically synthesizes RTL implementations from high-level design descriptions, including recently announced support for SystemC. Bluespec's integration with Sequence's PowerTheater allows ESL Synthesis to generate multiple trial configurations and then run PowerTheater to estimate power at RTL and, later, at the gate level. The generated power data allows users to examine tradeoffs for performance, area, and power to optimize the design's power profile early in the design cycle.

"Bluespec is on a mission to reduce the cost, time to market, and complexity of SoC design," said Sequence president and CEO, Vic Kulkarni. "Today, people use power estimates to spec the design, because it's typically too hard to change by the time they can get an RTL assessment - what they need is early and frequent feedback before they lock in the particular macro/micro architectural approach, which is precisely what can now be done by using PowerTheater in the ESL flow."

The integrated solution is currently available for users of Sequence and Bluespec products.

PowerTheater is the industry standard for low-power design at RTL.

Capabilities include accurate RTL power analysis closely correlated to actual silicon; power management tools that allow designers to reduce power at RTL using "what-if" scenarios and make early tradeoffs at the architectural level; power vector forward technology to select vectors for downstream analysis, feeding them to later stages of the design cycle for gate-level verification and voltage-drop analysis; and gate-level power verification, preventing power creep.

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