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Cadence extends flow support of ARM processors

Posted: 18 May 2006     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  Reference Methodology  ARM  processor  Cortex-R4 

Cadence Design Systems Inc. has expanded its Reference Methodology flow support of ARM processors to include the Cortex-R4 processor. The expanded Reference Methodology is the latest result of the close collaboration between Cadence and ARM.

The extended ARM-Cadence Encounter Reference Methodology now supports the ARM Cortex-R4 processor, Cortex-M3 processor, and all ARM7, ARM9 and ARM11 processor families.

"This expanded, jointly developed Reference Methodology provides our mutual customers with the value of quick core adoption," said Keith Clarke, vice president of technical marketing director at ARM. "This is an important vehicle for use with our Cortex-R4 processor, which targets embedded real-time systems for mass storage, automotive, industrial and networking applications."

The expanded ARM-Cadence Encounter Reference Methodology offers numerous benefits for ARM processor-based SoC designs. The flow has been pre-validated with ARM Artisan Physical intellectual property (IP) and is designed to reduce the effort required to implement ARM synthesizable processor IP, while the silicon-proven Cadence Encounter digital IC design platform helps deliver predictable results.

The ARM-Cadence Reference Methodology offers signal integrity analysis and repair to minimize risk and speed time to volume. It generates models required for end users to integrate ARM processors into their SoCs. Cadence technologies supported in this Reference Methodology include Cadence SoC Encounter, an integrated RTL-to-GDS hierarchical chip implementation system designed for large-scale and low-power designs. The fully-scripted flow also allows user customization where required.

The ARM-Cadence Encounter Reference Methodology provides a predictable route to silicon and a basis for customer methodology development using both logical and physical technologies. It enables rapid technology-specific implementation and streamlines the development of designs based on ARM processors. By delivering a powerful, automated RTL-to-GDSII implementation flow for ARM Partners, the methodology increases nanometre design efficiency and reduces time to silicon with predictable performance, power and area results.




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