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ADC designed for high-efficiency wireless, cable apps

Posted: 30 Mar 2006     Print Version  Bookmark and Share

Keywords:AD9230  ADC  analogue-to-digital converter  Analog Devices  Janine Love 

Analog Devices Inc. (ADI) puts a lot of muscle behind its converter product lines, and the AD9230 is one example of how the company has pushed the performance envelope lately. The AD9230 ADC is designed to bring greater efficiencies to wireless infrastructure and reduced power consumption and footprint to cable applications. It demonstrates specifications of 65.5dBfs SNR and 425mW power dissipation while handling 250MSps. And, particularly important for cable applications, with the 170MSps version, power dissipation drops to 350mW.

"For wireless applications, the AD9230 is designed to address concerns from our customers about implementing PA pre-distortion schemes over a wider signal bandwidth which requires sampling rates up to 245MSps for 3G, 3.5G and WiMAX applications," explained Jon Hall, strategic marketing manager, high-speed converters group. "In these systems, implementing these digital efficiency techniques reduces the overall transmit sub-system cost and allows system providers to differentiate themselves in the marketplace."

So, the team at ADI ensured that the 12bit AD9230 could achieve a 170/210/250MSps rate, and could demonstrate a spurious free dynamic range of 82dBc at the highest sampling rate in order to support PA linearization.

Form factors are also becoming more important in wireless infrastructure applications; the latest WiMAX base station designs are smaller than their wireless infrastructure counterparts. In response to this, the team at ADI designed the AD9230 into an 8-by-8mm 56-pin package.

For cable applications, the AD9230 was optimised for power as well as size, "because a key consideration here is the ability to put more devices on a single PCB in order to support future channel growth," said Hall. For cable applications, the team also worked to provide good SNR performance (65.5dBfs at 70MHz) in order to satisfy DOCSIS requirements.

The AD9230 is not a first generation product, but it grew out of the company's AD9430, a 210MSps device announced in 2002. The design team at ADI began work on the AD9230 in response to customer demand for a faster ADC in order to digitize a wide band of signals to implement predistortion techniques and ultimately improve the efficiency of the PA, particularly in 3G wireless systems. For wired broadband, customers needed a faster A/D in order to support digital telephony, as upstream or reverse-path cable traffic began to engulf the available bandwidth. In the case of cable applications, the AD9230 would typically be used in the cable modem termination system, where heat dissipation is an ongoing design challenge. Therefore, optimising power consumption became critical for success in this application.

The AD9430 released in 2002 was manufactured using a BiCMOS process, which enables fast linear blocks in the first stage of the converter. The AD9230, however, was designed on a 0.18 CMOS process, so the team was forced to develop some inventive design techniques to handle the input frequency at a fast sample rate. While CMOS allowed the team to drive down power consumption, the challenge was to maintain first-stage linearity. While Hall would not reveal any secrets here, he did report that a lot of intellectual property was developed with this design.

The AD9230 begin sampling in May 2006, with production scheduled to begin in September 2006. The 12bit AD9230 is priced at Rs.2,610.75 ($59) (250MSps), Rs.2,079.75 $47 (210MSps) and Rs.1,548.75 ($35) (170MSps) in 1,000-unit quantities.

- Janine Love

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