Cadence contributions to SystemVerilog standard recognised

Cadence Design Systems Inc. has announced that the IEEE has recognised Cadence for its contributions to the IEEE 1800 SystemVerilog standard. Nine Cadence technologists received awards for a wide range of improvements during the development of the SystemVerilog standard.

The Chairman's award went to Vassilios Gerousis and Francoise Martinolle. Gerousis was recognized for architecting the combination of HVL and HDL and driving it from conception to reality. Martinolle was recognized as one of the SystemVerilog champions leading the resolution of many issues among the various technical committees. Certificates of Recognition were awarded to Victor Berman, Charles Dawson, Steven Dovich, Jay Lawrence, Kathy McKinley, Steven Sharp and Jim Vellenga, who chaired or served on several special task forces and committees.

"The IEEE 1800 SystemVerilog Working Group is pleased to recognise Cadence leadership and contributions," said Johny Srouji, chair of the IEEE 1800 SystemVerilog Working Group. "The quality of the SystemVerilog language was significantly improved by Cadence's work and experience delivering standards."