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Xilinx, CMC increase IP development in India

Posted: 03 Mar 2006     Print Version  Bookmark and Share

Keywords:Xilinx  CMC  Hyderabad  IP  core 

Xilinx Inc., a U.S.-based supplier of programmable ICs, has revealed that its India development centre, operated by CMC Ltd in Hyderabad, has delivered 24 Intellectual Property (IP) cores since its establishment in February 2004.

All 24 India-designed IP cores are verified and optimised for use with Xilinx programmable silicon platforms. These are available to the company's worldwide customer base of over 7,500 companies.

Having doubled the size of the team to 60 in 2005, the Xilinx-CMC India development centre focuses on designing IP cores for automotive electronics, embedded processing, and high-speed serial I/O connectivity. The activities in Hyderabad cover all phases of the development lifecycle, including architecture specification, design, verification and hardware validation of IP cores.

"By investing early in India to incorporate it into our global R&D efforts, we have built a competitive advantage in utilizing the local engineering talent to create leading-edge IP solutions for our customers worldwide," the press release quoted Wim Roelandts, chairman, president and CEO of Xilinx. "Through our strategic relationship with CMC, our development activities in India have met our expectations and we will continue to leverage this exciting market as a source of innovation, talent and partnerships," he added.

"The growing success of the high value-added development activities in Hyderabad is a strong vote of confidence for Xilinx, CMC, and the local semiconductor industry," said Mr. Akshya Prakash, managing director of the Xilinx-CMC India development centre.

The Xilinx-CMC India development centre has over the past two years expanded the library of Xilinx-developed IP cores by 15%, which includes:

  • The CAN LogiCORE IP, which allows Controller Area Networks (CAN) protocol with the Xilinx Spartan and Virtex Platform FPGAs.
  • The PLB DDR2 SDRAM controller, which allows interfacing of the Virtex-II Pro and Virtex-4 PowerPC 405 cores to DDR2 memory through the PowerPC processor local bus.
  • The Aurora Protocol Specification v1.3 Bus Functional Model (BFM), which is an open, scalable, lightweight, link-layer protocol used to move data across point-to-point serial links.

- EE Times India

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