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MIPS introduces multithreading solution for embedded apps

Posted: 13 Feb 2006     Print Version  Bookmark and Share

Keywords:MIPS32  34K  processors  multithreading  MIPS Technologies 

Processor architectures are beginning to hit performance ceilings both in terms of shrinking substrate geometry and increasing clock speeds. Consequently, engineers have to look at other ways to maintain Moore's Law besides the traditional route of raising CPU frequency and/or shrinking circuit geometries, a prospect facing huge technological and cost challenges beyond 65nm.

An alternative approach is offered by MIPS Technologies with the introduction of its MIPS32 34K family of cores, a multithreading solution for embedded applications. The 34K core family is said to be the first to implement the MIPS MT ASE and leverages the proven 24KE micro-architecture that includes the MIPS DSP ASE.

The company has announced early adopter licencees including iVivity, Mobileye and PMC-Sierra. Single-threaded microprocessors waste many cycles while waiting to access memory, considerably limiting system performance. Dual core processors consume too much power and require double the die area, which makes them unsuitable for embedded applications. 34K cores aim to mask the effect of memory latency by increasing processor utilisation.

As one thread stalls, additional threads are instantly fed into the pipeline and executed, resulting in a gain in application throughput. Users can allocate dedicated processing bandwidth to real-time tasks resulting in a guaranteed QoS. This mechanism constantly monitors the progress of threads and dynamically takes corrective actions.

The MIPS 34K core offers its performance gains in application throughput using a multithreading, single issue, nine-stage pipeline with a modest increase in die size. The product does this by preserving legacy software investment and requires minimal or no changes to the application code.

QoSLogic is said to ensure the smooth operation of the processor core and its threads with minimal overhead. It is touted to have real-time capabilities and is able to allocate processing bandwidth to real-time tasks and low-latency interrupt handling.

The 34K core exhibits itself either as one or two virtual processor elements (VPE) or with up to five thread contexts (TC). VPEs act as completely separate processors and are an instantiation of the OS-only state of the MIPS architecture. As a result, the 34K can run two operating systems concurrently, standard or real-time or both.

The TC is an instantiation of the user-state of the MIPS32 architecture and allows software threads to run within an OS. A TC offers sufficient context to run a block of application code. Multiple processes/threads can be run concurrently. The user allocates processing bandwidth to the TCs while the QoSLogic hardware assigns priorities to TCs, monitors progress and dynamically takes corrective actions as needed. This enables dynamic assignment of processor resources for guaranteed real-time performance.

To demonstrate the performance advantage of the 34K core, when compared to the earlier MIPS 24KE core, a 60 per cent speed improvement using just two threads, with little effect on caches, has been demonstrated. Die impact was a 14 per cent increase in area.

The 34K cores can run existing two-way SMP operating systems and applications with minimal changes. But it can also be used in environments where independent concurrent threads have very different roles ("AMP" or asymmetric multiprocessing). Additionally, the 34K cores can be configured with a maximum of two VPEs and five TCs for ultimate design flexibility. This dual VPE capability allows the 34K cores to run two independent operating systems concurrently or alternatively a two-way SMP OS. In addition, up to five TCs can be used to allow a single OS to run up to five processes concurrently.

- Jean-Pierre Joosting

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