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Epson develops "smallest" gate array

Posted: 06 Feb 2006     Print Version  Bookmark and Share

Keywords:S1L50000  gate arrays  WCSP  wafer level chip size package  Seiko Epson 

Seiko Epson Corp. (Epson) claims to have developed the world's smallest gate array. By utilizing a wafer level chip size package (WCSP) with a size of 2.41 by 2.41mm (when using the WCSP for S1L5012), the company said that they have succeeded in achieving the world's smallest package size and mounting area for a gate array product.

The gate array products in the S1L50000 series offer a range of products with a diverse set of gate numbers. All the products are compatible (core voltage: 3.3V, I/O voltage: 5V, current consumption:0.7μW/MHz/BC) with those in the existing S1L50000 series, so they can be used in the same types of operating environments.

By utilizing the WCSP, Epson said they were able to reduce the size of the gate arrays in the current S1L50000 series to as little as 30 per cent of their current size. These products can be used in applications such as card devices, portable devices and other equipment for which mounting area is limited.

The company added that the use of ASICs has allowed them to have a short turn around time for sample delivery and support for transition to volume production. The line-up has also been expanded to include QFN and TQFP gate arrays, as well as WCSPs in response to the demand for smaller mounting areas and compliance with various mounting conditions.

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