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Cadence offers silicon-proven full-chip optimisation system

Posted: 06 Feb 2006     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  chip  Chip Optimizer 

Cadence Design Systems Inc. has announced its manufacturing-aware chip optimisation product, Cadence Chip Optimizer, which is a silicon-proven full-chip optimisation system. Cadence Chip Optimizer is used after conventional place and route, and before design tape out to improve the yield, manufacturability and performance of complex IC designs.

Cadence developed Chip Optimizer as part of its growing family of manufacturing and yield-aware offerings aimed at addressing the industry's most pressing design for manufacturing (DFM) and design for yield (DFY) challenges. It uses a three-dimensional space-based optimisation approach which models, analyses and optimises true shapes and intervening physical spaces. This provides a more accurate and realistic 'map' of the design, and clearly indicates where important optimizations may be made, explained the company. Shapes and spaces can be positioned in the exact configuration and location required to correct for sub wavelength, spacing and topological effects, thus enables greater precision and flexibility in optimisation.

The Cadence Chip Optimizer technology performs interconnect topology optimisations, while taking into consideration manufacturing and electrical constraints on digital or custom designs.

"Unlike many contemporary technology developments purporting to solve manufacturability issues at advanced process nodes, this product represents a fundamental breakthrough in chip scale physical and electrical modelling," said Ted Vucurevich, CTO of advanced research and development at Cadence. "Integrated with incremental sign-off quality analysis and advanced optimisation capability, this technology allows us to accurately handle today's most demanding sub-wavelength lithography and manufacturing process rules, and sets the stage to efficiently evolve our capabilities in accordance with the currently published International Semiconductor Association roadmap."

The Cadence Chip Optimizer works seamlessly with the Cadence Encounter digital IC design platform and the Virtuoso custom design platform. It is a native application on the OpenAccess database.




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