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TSMC starts 80nm "half-node" process technology

Posted: 23 Jan 2006     Print Version  Bookmark and Share

Keywords:80nm  TSMC  Taiwan Semiconductor Mfg Co. 

Taiwan Semiconductor Mfg Co. (TSMC) announced that it has entered full production of its 80nm "half-node" process technology. With this process, TSMC claims that designers can improve performance and reduce the overall size of their designs by up to 19 per cent, resulting in more die per wafer and more than 20 per cent cost-per-die reduction.

"TSMC offers the half-node as an extra option to our customers," said Jason Chen, VP of corporate development for TSMC. "The potential performance, die area and yield improvements, coupled with the cost-per-die savings, provide a clear competitive advantage and easy shrink path for our customers."

The 80nm process is a lithographic shrink of the 90nm process technology. As a consequence, this node supports most of 90nm TSMC and third-party libraries and IP requiring only simple re-characterisation using 80nm models. Design rules are also a linear shrink from 90nm. The result is said to be a significantly reduced re-design time to port the chip to the process.

The first 80nm process in production is TSMC's high-performance GT process, which will be followed next month by the high-speed HS process and low power LP processes in March 2006. A special GC process, which provides both low active and standby power advantage, will become available in Q3 of 2006.




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