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Single-ended to differential buffer serves single-supply A/Ds

Posted: 25 Aug 2005     Print Version  Bookmark and Share

Keywords:adc  differential buffer  analog devices  adi 

By Randall Carver, Analog Devices Inc.


DC coupling of single-ended signals into differential-input single-supply ADCs can be challenging. The input signal requires level shifting from ground to Vs/2 as well as single-ended to differential conversion. In addition, the differential inputs of the ADC must be balanced to cancel even order harmonics and common mode noise. Systems often require this signal translation to take place without injecting dc bias currents back into the signal source. Processing wideband signals with large dynamic range (12-/14-bit ADCs) can also add to the circuit complexity.

Wideband amplifiers such as the AD8351 address nearly all of these issues, but their standard implementation requires the use of ac coupling. This design idea describes a new circuit that eliminates this requirement through the use of an external dc feedback loop. It also allows the lower end of the pass band to extend to dc.

The basis of the circuit is the simple level shifting circuit shown in Figure 1. Tying two series resistors between Vs and a signal source attenuates the signal by 2 and biases it to Vs/2. The center tap is buffered, and can then be processed by single sided supply circuits. Two additional series resistors connected between the source and a negative supply of equal value removes dc bias currents from the source.

Figure 1: Level-shifting for ac signals

The circuit of Figure 2 expands upon this simple concept by replacing the supply voltages ±Vs with precise ±DC levels that track one another. In addition, differential signaling is implemented by doubling up the number of level shifting resistors. The ±DC levels are produced by subtracting the 2.4V ADC reference signal from the common mode level of the amplifier, which is formed by summing the two amplifier outputs through equal value resistors. The difference is amplified, filtered, and inverted to create the ±DC levels. The dc feedback loop gain of 1,040 allows the amplifier to track the output common mode level to within (2.4V/1040)= 2.3mV of the ADC VREF signal.

Figure 2: Wideband dc-coupled single-to-differential buffer

The addition of this external dc feedback path allows the VOCM pin to be opened and decoupled to ground, disabling the AD8351 internal dc feedback path. The level shifting resistors were set to a ratio of 1.09:1 in order to reduce the required swing of the ±DC levels to ±(2.4)[(1.09+1)/(1.09)] = ±4.6V. Accurate networks with excellent tracking are used to ensure good CMRR and minimize the injection of dc bias currents into the source. A rail-to-rail feedback amplifier is chosen for U2, allowing for the use of ±5V supplies. The remaining circuits are powered from 5V. The resistor Rg is used to vary the overall gain of the front-end.

For a front-end gain of 0dB, the bandwidth extends beyond 1GHz, as shown in Figure 3. After the required gain is determined, the resistor Rf is adjusted to balance the two differential signals into the ADC. Typical values of Rg and Rf are shown in Table 1 for various gain levels.

Table 1: Wideband dc-coupled single-to-differential buffer

The 64.9-ohm resistor provides for a 50-ohm source impedance. The 28-ohm resistor provides for a balanced input as seen from the amplifier. A differential input signal structure can be accommodated by replacing the 28-ohm resistor with a 64.9 ohm resistor, and tying the additional negative input signal to the junction of the new 64.9 ohm resistor and the two 240-ohm level shifting resistors. This differential input structure allows for the removal of Rf.

Figure 3: Frequency response with a 1k-ohm load

The excellent distortion performance of the AD8351 amplifier has been maintained within this design allowing 12- and 14-bit ADCs to be driven with minimal degradation to the ADCs dynamic range (Figure 4).

Figure 4: Harmonic distortion vs. frequency (for -1dBfs into AD6645 at 80MS/s)

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