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IP core replaces up to 16 ASICs

Posted: 03 Nov 2005     Print Version  Bookmark and Share

Keywords:rf engines  ddc core  fpga  ip core  channelcore64 

RF Engines introduced the first, fully flexible 64-channel digital down-conversion (DDC) core for use on FPGAs. The intellectual property (IP) core, known as the ChannelCore64 has also been announced as a winner of the GSPx New Product Forum Award.

ChannelCore64 allows designers to replace up to 16 specialist DDC ASICs with a single IP core for FPGAs, reducing board area, lowering power consumption, and increasing flexibility. The new approach is designed to enable a major cost saving over traditional methods, with savings becoming more significant as the number of channels increases. ChannelCore64 is targeted at applications such as wireless base stations, satellite ground stations, and other multi-channel radio receivers.

Key features include:

• Support for two 16-bit ADC inputs each with a sample rate up to 140 mega-samples per second.

• 64 independent down-conversion channels, which may be connected to either ADC.

• Independent tuning of channel centre frequencies with a resolution of less than 0.01Hz.

• Independent selection channel bandwidths.

• Independent selection output sample rates with a resolution less than 0.01Hz.

• Channel reconfiguration when core is running without affecting the operation of other channels.

A bit-true Matlab model is available so designers can accurately simulate ChannelCore64 within their system context. The core is supplied under a simple licensing model, and custom variants, including up-converters, can be produced on request.

- Janine Love


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