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FPGA development tool upgraded with new simulation capability

Posted: 18 Nov 2005     Print Version  Bookmark and Share

Version 5.1 of the DSP Builder development tool from Altera Corp. is designed to enable FPGA designers to simulate an imported HDL design within The MathWorks Simulink environment, which the company claims is a first for model-based design. By combining their own HDL-based designs with existing Simulink and DSP Builder models, designers of high-speed digital applications can assist in cutting development time, said Altera.

An important ingredient of model-based design is the ability to simulate systems with HDL-based blocks," said Ken Karnofsky, marketing director for signal processing and communications at The MathWorks, in a statement. "Altera has created a platform for high-speed DSP development on FPGAs that can shorten the verification process."

DSP Builder allows engineers to reduce the DSP design cycle by creating a hardware representation of a DSP design in an algorithm-based environment. With the tool, designers can incorporate multiple HDL modules or Quartus II software design projects simultaneously. An individual simulation model can be generated for each one, allowing designers to simulate the HDL modules with a standard Simulink/DSP Builder-based model in the same design environment.

The tool also makes it possible to reuse existing designs, which is critical for simulating large control logic or complex state machine subsystems together with DSP Builder's DSP data path.

DSP Builder v5.1 is available to customers with a current DSP Builder subscription. Subscription pricing is $1,995. This includes 12 months of software upgrades.

- Ismini Scouras


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