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Plato unwraps router for huge systems-on-chip

Posted: 01 Jun 2001     Print Version  Bookmark and Share

Keywords:nanoroute  def  lef  system on chip  soc routing 

Proclaiming a breakthrough in SoC routing, startup Plato Design Systems took the wraps off NanoRoute, a "scalable" IC router that claims to eliminate capacity bottlenecks. A single solution for detailed block-level routing and chip-level assembly, NanoRoute uses Plato's distinctive "graph-based" technology.

Plato was founded in 1999 by Limin He, president and CEO and David Yao, VP of R&D. The company promises concurrent routing and 3D extraction, but the extraction capability is not available in the first release of NanoRoute.

Plato claimed NanoRoute could run up to 10 times faster than gridded routers, while offering the flexibility of shape-based routers. Capacity requirements are said to scale linearly with circuit complexity and parallel processing can accelerate both detailed and global routing. "If designers invest in this solution, they will not have to worry about capacity limits for their next project," said Joe Xi, Plato vice president of marketing.

Chip routers today, Xi said, fall into two categories: gridded and gridless. Gridded routers are fast and high capacity, Xi said, but they cannot handle non-uniform design rules. When metal pitches are non-uniform and variable wire width and spacing are needed, gridded routers run into trouble, he said.

Gridless routers deal with shapes rather than grids and have much more flexibility. But, Xi said, these routers are slow and quickly run into capacity limits. Like gridded routers, Plato's graph-based approach partitions the routing into fine increments. But, said Xi, "we do not use a uniform grid. We treat the routing space as a general graph. A graph is a generalization of a grid or any geometry. The advantage is that we have a more efficient way to represent the routing space."

Best of both worlds

The new approach promises the best of both worlds. NanoRoute is "orders of magnitude" faster than shape-based routers and typically two to three times faster than gridded routers, Xi said.

"For cell- and block-based design, our flexibility should be the same as a shape-based router," Xi said. NanoRoute, for example, can wire off the grid and support variable wires and spacing to meet signal-integrity concerns.

Xi said NanoRoute is also unique in its ability to handle both chip-level assembly and detailed cell-level routing. Xi, however acknowledged that NanoRoute does not yet does power or clock routing but said that it would be available in future releases.

Plato has a patent-pending global routing algorithm, Xi said, that allows runtime and memory to increase only linearly with the number of nets. Further, both detailed and global routing can be accelerated by the use of multiple CPUs.

Xi said the company has tried up to 16 CPUs thus far, and experienced a ten-fold to twelve-fold speed up. According to one company benchmark, a 250MHz Sun Enterprise 4000 with 10 CPUs routed a 505,000-cell design with 501,000 nets in 19min.

Designers can link NanoRoute to existing placement and routing systems through the Cadence Library Exchange Format (LEF) and Design Exchange Format (DEF).

The concurrent 3D extraction, along with delay calculation and timing analysis, would probably come with a new product to be introduced after this year's design automation Conference, Xi said.

With prices starting at $300,000, NanoRoute does not come cheaply. It is shipping now and Fujitsu Microelectronics is Plato's first announced customer.

Richard Goering

EE Times

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