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EE Times-India > EDA/IP

Co-verification speeded up for design

Posted: 16 Jun 2001     Print Version  Bookmark and Share

Keywords:ipc  verification  vcpu  gui  xcite 

Innoveda Inc. boosted the performance of its V-CPU hardware/software co-verification system through a link with Axis Systems' simulation accelerator and emulator.

The latest spin of V-CPU, version 4.0, formally integrates Xcite and xtreme, Axis' simulation accelerator and emulator, said Steve Anderson, Innoveda's product-marketing manager for hardware/software co-design tools. The result is an increase in the performance of the hardware portion of the co-verification process, he said.

"We have had mutual customers in the networking space that used our solutions together," said Yukari Chin, director of marketing at Axis. "But now we have gotten together to make them work together more efficiently."

Anderson said Innoveda added to V-CPU a new interprocess communication (IPC) mechanism that allows V-CPU and Axis verification systems to share memory, when applicable. This makes the hardware end of the verification 30 percent faster than the previous version of V-CPU, version 3.12, linked to the same Axis hardware-assisted verification products, Anderson said. "If two processes are running on the same machine, we can now use shared memory instead of sockets," he added.

Rendezvous mechanism

Innoveda also changed the rendezvous mechanism between software and hardware, Anderson said. "There are times when the hardware checks to see if there is a pending request from the software. The previous version every time it tried to rendezvous did an IPC call from the hardware to software. With the new version, we eliminated that and now we just do a software semaphore—the hardware checks out the points where it is looking for software."

Anderson said the company has also improved the graphical user interface to simplify the hardware/software co-verification process in designing embedded-system applications. "Software people are largely unfamiliar with hardware simulation tools like Verilog simulators," he said. "They can use an environment that handles a lot of the integration issues for them."

The new GUI has a spreadsheet to configure the hardware side. "It allows them to tell the tool what details they want to run hardware simulation on, when to start it and allows them to monitor it if they wish," said Anderson. "It allows them to get to software testing quicker."

In addition, the tool also supports transaction debug functions such as single stepping and break-pointing, which can be monitored from a centralized interface.

Also in response to requests from software developers, V-CPU now supports Windows 2000, Red Hat Linux platforms and multi-threaded software applications.

Also in response to requests from software developers, V-CPU now supports Windows 2000, Red Hat Linux platforms and multi-threaded software applications.

Michael Santarini

EE Times

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