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Intel StrataFlash wireless memory (L18 SCSP) to ARM PrimecellTM SMC (PL092) design guide

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Intel StrataFlash.

Wireless Memory

(L18 SCSP) to ARM.

PrimecellTM

SMC (PL092) Design Guide

256-Mbit L18 with 64-Mbit PSRAM

Application Note 801

June 2004

Order Number: 302751-001

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not

finalize a design with this information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright ) 2004, Intel Corporation

*Other brands and names may be claimed as the property of others.

3

AP-801

Contents

1.0 Introduction ..................................................................................................................5

1.1 Intel StrataFlash. Wireless Memory (L18 SCSP) Feature Overview ...................5

1.2 ARM. Primecell SMC (PL092) Feature Overview................................................5

2.0 Hardware Interfaces..................................................................................................6

2.1 L18 SCSP Interface...............................................................................................6

2.2 Static Memory Controller Pad Interface ................................................................9

3.0 Interface Considerations.......................................................................................11

3.1 Hardware Connections........................................................................................11

3.2 Flash Configuration Register...............................................................................12

3.3 PSRAM Configuration Registers.........................................................................12

3.3.1 PSRAM Refresh Control Register ..........................................................13

3.4 Memory Controller Registers...............................................................................13

3.4.1 Bank Registers.......................................................................................14

4.0 Bus Interface Timing...............................................................................................15

4.1 Asynchronous Single Reads ...............................................................................15

4.2 Asynchronous Page Mode Reads.......................................................................17

4.3 Asynchronous Writes ..........................................................................................18

4.4 Write Buffer Programming...................................................................................20

4.5 Concurrent Write Buffer Operations ....................................................................21

5.0 Summary......................................................................................................................21

Appendix A Additional Information ........................................................................................22

4

AP-801

Revision History

Date of

Revision

Version Description

6/17/04 -001 Initial Release

AP-801

Application Note 5

1.0 Introduction

This application note describes interfacing Intel StrataFlash.

Wireless Memory (L18 SCSP),

featuring 256-Mbit L18 flash memory with 64-Mbit Synchronous PSRAM, to an Advanced RISC

Machines Limited (ARM.

) PrimecellTM

Static Memory Controller (SMC - PL092). The SMC

supports asynchronous flash memory, SRAM, and PSRAM.

The application note assumes that you have a working knowledge of L18 SCSP and ARM

Primecell peripherals, and familiarity with memories such as flash, SRAM, and PSRAM.

This document is based on information available at the time of publication. Subsequent changes to

specifications may not be reflected in this document. The interface described here has not been

implemented in hardware. Check with your local Intel sales office for the latest Intel product

information before finalizing any design.

1.1 Intel StrataFlash.

Wireless Memory (L18 SCSP) Feature

Overview

Intel StrataFlash. Wireless Memory is a Stacked Chip-Scale Package (SCSP) solution. It

combines a 256-Mbit Intel StrataFlash. Wireless Memory (L18) die with a 64-Mbit synchronous

pseudo SRAM (PSRAM) die. The L18 SCSP device incorporates fourth-generation Multi-Level

Cell (MLC) and Intel 0.13 5m ETOXTM

VIII process technologies.

7 The L18 flash memory die features flexible, multi-partition, dual operation for Read-While-

Write and Read-While-Erase performance. Also featuring Asynchronous Page and

Synchronous Burst Read modes, the L18 die is ideal for executing code in place (XIP). Other

features include a 54 MHz maximum burst clock rate and Burst Suspend.

7 The PSRAM die features Asynchronous Page and Synchronous Burst mode read and write, as

well as partial array refresh, programmable output impedance, and up to 66 MHz maximum

burst clock rate.

The L18 SCSP device is available in the QUAD+ package, providing easy migration or upgrade to

other Intel SCSP families. The 8x10 active-ball matrix of the QUAD+ signal ballout has 0.8 mm

pitch with a 8 x 11 x 1.2 mm package.

See the Intel StrataFlash. Wireless Memory (L18 SCSP) datasheet for additional details; this is

listed in Appendix A, "Additional Information".

1.2 ARM.

Primecell SMC (PL092) Feature Overview

ARM Primecell peripherals are macrocell modules developed by Advanced RISC Machines

(ARM.

) to enable rapid development and assembly of System-on-Chip (SoC) products such as

application processors and communications chipsets. ARM Primecell Peripherals are ready-to-use

soft-IP solutions, fully verified and compliant with the Advanced Microcontroller Bus Architecture

(AMBATM

) on-chip bus standard available from ARM (www.arm.com).

The ARM Primecell Static Memory Controller (SMC) is a peripheral interface designed for use

between an ARM Advanced High-Performance Bus (AHB) and external static memory. The SMC

supports up to eight memory banks with a Chip Select for each bank that is configurable to be

AP-801

6 Application Note

either active HIGH or active LOW (default). Each Chip Select can be configured for x8, x16 or x32

asynchronous static memory devices. Supported asynchronous devices include SRAM, ROM, and

flash (including page-mode flash). Each Chip Select is capable of addressing up to 64 MBytes of

memory.

The SMC boots from asynchronous non-volatile memory such as ROM or flash memory (bottom-

boot). During boot-up, memory bank 7 is used, therefore chip select SMCS7 is used to access the

boot code at address 0x0000 0000. The SMC provides additional input signals that are sampled at

boot-up for configuring the boot chip select bus width (SMMWCS7[1:0]).

See the ARM Primecell Synchronous Static Memory Controller (PL093) Technical Reference

Manual for additional information regarding the ARM Primecell SMC; this document is listed in

Appendix A, "Additional Information".

2.0 Hardware Interfaces

The following sections describe the L18 SCSP - SMC hardware interface. They assume that you

are using the SMC in an Application-Specific Integrated Circuit (ASIC) design with compatible

I/O voltage levels, and that all other signals are connected for proper operation.

2.1 L18 SCSP Interface

L18 SCSP integrates several high-performance features including:

7 Read Configuration Register (RCR)

7 Address Latch (ADV#)

7 Internal burst-address generator

7 Programmable WAIT polarity

The Read Configuration Register (RCR) configures the L18 flash memory die for specific interface

controller characteristics. These include the read mode (synchronous or asynchronous),

synchronous burst length (4, 8, 16, or continuous data), initial-access latency, active clock edge

polarity, and WAIT-asserted output signal polarity.

The address valid signal (ADV#) is used to latch the initial address during synchronous burst read

operations. It can also be used with an address/data multiplexed bus (A/D-Mux) to de-multiplex the

bus signals.

The RCR settings notify the internal burst-address generator how to generate the addresses during

synchronous burst-mode reads. Generating the addresses internally eliminates memory dependence

on the memory controller for new addresses during burst reads, hence improving system read

performance.

The WAIT output signal is provided for flash-to-controller communication and synchronization

during synchronous burst-mode reads. It drives the memory controller Data Ready input, and

notifies its Wait-state generator when a delay is needed, for example, during the initial-access

latency of a synchronous burst-read operation.

AP-801

Application Note 7

Figure 1 is a block diagram of the L18 SCSP device. Table 1 lists the signals and their descriptions.

See the Intel StrataFlash. Wireless Memory (L18 SCSP) datasheet for detailed information

regarding signals not shown.

Figure 1. L18 SCSP Block Diagram

Table 1. L18 SCSP Signal Descriptions (Sheet 1 of 2)

Signal Name Type Description

A[23:0] Input

ADDRESS: Device address inputs for all dies. 256-Mbit flash die uses A[23:0]; 64-Mbit

PSRAM die uses A[21:0].

D[15:0] Input/Output

DATA I/O: Inputs data and commands during write operations (WE#-low), and outputs data

during read operations (OE#-low). D[15:0] are High-Z when chip enables or output enables

are deasserted.

F1-CE#

P-CS#

Input

CHIP ENABLE: Low-true. F1-CE# asserted selects the flash die, while P-CS# asserted

selects the PSRAM die. When both chip selects are deasserted, the dies are placed in

standby, and D[15:0] and WAIT are placed in High-Z.

F1-OE#

R-OE#

Input

OUTPUT ENABLE: Low-true. F1-OE# asserted enables the D[15:0] output buffers of the

flash die, or R-OE# asserted enables the D[15:0] output buffers of the PSRAM die. When

both output enables are deasserted, the output buffers of both die are deselected, placing

D[15:0] and WAIT in High-Z independent of CHIP ENABLE. F1-OE# and R-OE# may be tied

together and driven by the same source.

F-WE#

R-WE#

Input

WRITE ENABLE: Low-true. F-WE# asserted enables data writes to the flash die (F1-CE#

asserted), while R-WE# asserted enables data writes to the PSRAM die (P-CS# asserted).

Data is latched on the rising edge of WRITE ENABLE with CHIP ENABLE asserted. F-WE#

and R-WE# may be tied together and driven by the same source.

R-UB#

R-LB#

Input

PSRAM UPPER/ LOWER BYTE ENABLE: Low-true. During PSRAM read and write bus

cycles, R-UB# asserted and/or R-LB# asserted enables the upper and/or lower bytes on

D[15:8] and D[7:0], respectively.

28F256L18

Flash

64-Mbit

Synchronous

PSRAM

A[23:0]

D[15:0]

F1-CE#

P-CS#

F1-OE#

F-WE#

F-WP#

F-RST#

CLK

ADV#

WAIT

R-WE#

P-CRE R-OE#

R-UB#

R-LB#

A[23:0]

A[21:0]

AP-801

8 Application Note

CLK Input

CLOCK: Bus clock input used to synchronize flash synchronous read operations, and

PSRAM synchronous read/write operations.

For synchronous flash and PSRAM operations, the initial address is latched on the first active

clock edge when ADV# is low. CLK also increments the internal burst-address generator.

For asynchronous flash operations, CLK is ignored; for asynchronous PSRAM operations,

CLK must be held low. If only asynchronous flash and PSRAM operations are used, CLK can

be tied low.

ADV# Input

ADDRESS VALID: Low-true. ADV#-low indicates a valid address on A[23:0].

For flash synchronous read mode and PSRAM synchronous read/write modes, the address

of the initial access is latched on the rising edge of ADV# or the next valid edge of CLK while

ADV# is low, whichever occurs first.

For all asynchronous read/write modes, ADV# can be used to latch the address, or remain

low throughout the access.

WAIT Output

WAIT: Configurable high-true or low-true. WAIT-asserted indicates invalid data, and can be

used to determine when additional delay is needed (e.g., during initial access, boundary

crossings, self-refresh cycles, etc.). WAIT is driven by the selected die (flash or PSRAM), and

is High-Z whenever CHIP ENABLE or OUTPUT ENABLE is deasserted.

Flash: During synchronous flash reads, WAIT-asserted indicates invalid data. During

asynchronous reads and writes, WAIT is deasserted, and should be ignored.

PSRAM: During synchronous PSRAM reads, WAIT-asserted indicates invalid data. During

asynchronous reads and writes, WAIT is not used and should be ignored. During

synchronous writes, WAIT-deasserted indicates when the write input data must be valid.

P-CRE Input

PSRAM CONTROL REGISTER ENABLE: High-true. Used in conjunction with address bit

A19 to program the PSRAM Refresh Control Register (P-RCR, A19 = 0) or Bus Control

Register (BCR, A19 = 1).

F-WP# Input

FLASH WRITE PROTECT: Low-true. When low, F-WP# enables the lock-down protection

mechanism - locked down blocks cannot be unlocked with software commands. When high,

F-WP# disables the lock-down protection mechanism, allowing locked blocks to be unlocked

using software commands.

F-RST# Input

FLASH RESET: Low-true. RST#-low resets all flash internal automation and inhibits write

operations. This can provide data protection during power transitions. RST#-high enables

normal flash operation. Exiting from reset places the flash die in asynchronous read-array

mode.

Table 1. L18 SCSP Signal Descriptions (Sheet 2 of 2)

Signal Name Type Description

AP-801

Application Note 9

2.2 Static Memory Controller Pad Interface

The ARM.

Primecell Static Memory Controller (SMC) provides a pad interface for connection to

off-chip asynchronous static memory devices. Final implementation of a Primecell-based memory

controller in an ASIC design depends on product requirements; not all available PrimeCell

interface signals may be used in the final design.

Actual signal names may vary depending on how the ASIC designer decides to implement the

ARM Primecell blocks described in this document. Also, in order to reduce the package size and/or

final pin count, ASIC designers might multiplex certain memory controller signals, such as byte

lane selects, output enables, write enables,..., onto the same pins.

Figure 2, "Static Memory Controller Block Diagram" on page 9 shows the SMC memory

controller. Table 2, "Static Memory Controller Signal Descriptions" on page 10 lists the signals

used in this design and their descriptions. See the ARM.

Primecell SMC Static Memory Controller

(PL092) Technical Reference Manual for additional information regarding the ARM Primecell

SMC signals; see Appendix A, "Additional Information".

Figure 2. Static Memory Controller Block Diagram

Pad Interface

AHB

Master

Interface

AHB

Slave

Interface

SMADDR[25:0]

SMDATAOUT[31:0]

SMDATAIN[31:0]

nSMWEN

nSMOEN

nSMDATAEN[3:0]

nSMBLS[3:0]

HSIZE[2:0]

HADDR[28:0]

HTRANS[1:0]

HRDATA[31:0]

HRESPTIC[1:0]

HRDATATIC[31:0]

HGRANTTIC

HTRANSTIC[1:0]

HADDRTIC[31:0]

HREADYIN

nHCLK

TESTREQA

TESTREQB

TESTACK

Test

Signals

AHB

Interface

Signals

HCLK

HRESETn

HWRITE

HBURST[2:0]

HWDATA[31:0]

HRESP[1:0]

HSELSMC

HREADYOUT

HSELREG

HWRITETIC

HSIZETIC[2:0]

HBURSTTIC[2:0]

HWDATATIC[31:0]

HPROTTIC[3:0]

HBUSREQTIC

SMCS[7:0]

Static Memory

Controller (SMC)

Async/Sync

Flash, SRAM

Control

Signals

Shared

Bus

Signals

(PL092)

SMWAIT

CANCELSMWAIT

SMMWCS7[1:0]

SMRBLECS7

Boot

Configuration

HLOCKTIC

AP-801

10 Application Note

Table 2. Static Memory Controller Signal Descriptions

Signal Name Type Description

SMADDR[25:0] Output ADDRESS BUS: Memory address bus to external memory banks.

SMDATA[31:0] Input/Output DATA BUS: External memory data bus to/from external memory banks.

SMCS[7:0] Output

CHIP SELECTS: Configurable chip selects (default active LOW) for each external

memory bank. SMCS7 is the boot chip select (see text).

nSMBLS[3:0] Output

BYTE LANE SELECT (active-LOW): nSMBLS[3:0] select byte lanes

SMDATA[31:24], SMDATA[23:16], SMDATA[15:8], and SMDATA[7:0], respectively,

when accessing external memory banks.

nSMOEN Output OUTPUT ENABLE (active-LOW): Read enable for external SMC memory banks.

nSMWEN Output WRITE ENABLE (active-LOW): Write enable for external SMC memory banks.

SMMWCS7[1:0] Input

MEMORY BANK 7 WIDTH SELECT: Width configuration setting for boot memory

bank 7.

SMRBLECS7 Input

MEMORY BANK 7 LANE SETTING: Indicates the memory device read byte lane

setting used for boot memory bank seven.

SMWAIT Input WAIT MODE: Wait indication from the external memory controller.

CANCELSMWAIT Input

WAITED TRANSFER RECOVERY: Enables the system to recover from an

externally waited transfer that take longer than expected to finish.

AP-801

Application Note 11

3.0 Interface Considerations

This section describes interfacing the L18 SCSP with the ARM.

Primecell Static Memory

Controller (SMC). Other device signals/pins should be asserted or negated as necessary for desired

device operation. Proper power supply voltages must also be applied in accordance with the latest

datasheet information.

This sample interface design does not include information regarding system initialization, interrupt

control, exception handling, or other peripheral device operations. Read all applicable

documentation, such as the datasheets, user manual, specification updates,..., before attempting this

interface.

3.1 Hardware Connections

Figure 3 shows a block diagram of the hardware connections between L18 SCSP and the ARM.

Primecell SMC. It is assumed that the system boots from flash memory using the SMC.

In the L18 SCSP device, the 256-Mbit Intel StrataFlash. wireless memory die is enabled by F1-

CE#, while the 64-Mbit synchronous PSRAM die is enabled by P-CS#. The address and data are

common to both die, while each die has its own x-OE# and x-WE# input. These inputs must be tied

together on the system board. See Figure 3, "L18 SCSP to ARM. Primecell Static Memory

Controller Hardware Connections" on page 11.

Figure 3. L18 SCSP to ARM.

Primecell Static Memory Controller Hardware Connections

ARM.-Based Chipset/ ASIC

ARM. SSMC

Memory Controller

SMADDR[24:1]

SMDATA[15:0]

nSMWEN

nSMOEN

SMCS7

F1-OE#

CLK

F1-CE#

D[15:0]

ADV#

A[23:0]

F-WE#

F-RST#

WAIT

System

Reset#

SMCS2 P-CS#

24

16

64-Mbit

Synchronous

PSRAM

R-OE#

R-WE#

Intel StrataFlash.

Wireless Memory (L18 SCSP)

nSMBLS1 R-UB#

R-LB#nSMBLS0

nRESET

28F256L18

Flash

Memory

P-CREGPIO (see text)

SMMWCS7[0]

SMRBLECS7

SMMWCS7[1]

AP-801

12 Application Note

Since the SMC only supports asynchronous operations, it does not use CLK, ADV#, and WAIT.

Input pins CLK and ADV# must be tied LOW; output pin WAIT must not be connected.

The PSRAM die uses P-CRE for access to its control registers, PSRAM-Refresh Control Register

(P-RCR) and Bus Control Register (BCR). Any available system general-purpose output (GPIO)

can be used to assert P-CRE when programming the PSRAM control registers.

On reset, the system boot code is accessed by the flash die using SMCS7. To provide the correct

external memory width (16-bit) at reset for bank 7, connect the external control pins as follows:

7 SMMWCS7[1] must be tied-HIGH

7 SMMWCS[0] must be tied-LOW

7 SMRBLECS7 must be tied-HIGH

Since the default memory width for bank 2 is 16-bit, in this example, SMCS2 is used to access the

PSRAM die. If other SMC memory banks (except bank 7) are used to access the SRAM die, their

memory bus widths should be programmed to 16-bit. Depending on individual system

requirements, memory mapping can change how the chip selects are allocated.

Refer to the ARM.

Primecell SMC Technical Reference Manual for additional information

regarding boot options and memory re-mapping.

3.2 Flash Configuration Register

On reset, the flash die defaults to Asynchronous Read-Array mode where reading from the flash

die returns array data. Asynchronous Page mode reads are allowed without requiring additional

commands.

The flash die also supports Synchronous Burst Read mode. To enable synchronous burst reads, the

flash Read Configuration Register (RCR) must be properly programmed. Synchronous burst-read

lengths of four, eight, sixteen, and continuous are supported by the flash die. Since ARM.

Primecell SMC does not support Synchronous Burst Read mode no programming is required for

the RCR.

Refer to the Intel StrataFlash. Wireless Memory (L18 SCSP) datasheet for additional information

on the Read Configuration Register.

3.3 PSRAM Configuration Registers

On power-up, the PSRAM die defaults to Asynchronous Read/Write mode. It also supports NOR-

Flash mode (Synchronous Read, Asynchronous Write) and Synchronous Read/Write mode. To

enable each mode, the PSRAM control registers, P-RCR and BCR, must be properly programmed.

To program the PSRAM control registers, P-CRE must be high while writing to the device. The

desired register setting (opcode) is placed on the address lines, and the level on A19 determines

which register is accessed: 0 = P-RCR, 1 = BCR. The data inputs are not used.

Since ARM Primecell SMC does not support Synchronous Burst Read mode no programming is

required for the BCR.

AP-801

Application Note 13

3.3.1 PSRAM Refresh Control Register

The PSRAM Refresh Control Register (P-RCR) configures Page mode and refresh operations, and

enables Deep Power-Down mode. Table 3 shows the available P-RCR settings. See the Intel

StrataFlash. Wireless Memory (L18 SCSP) datasheet for additional information on the PSRAM

Bus Control Register.

Notes:

1. A19 (Control Register Select) = 0b0 (P-RCR)

2. A7 (Page Mode): 0 = disabled (default); 1 = enabled

3. A[6:5] (Temperature-Compensated Self Refresh):

4. A4 (Deep Power Down Mode): 0 = enabled; 1 = disabled (default)

5. A[2:0] (Partial-Array Self Refresh)

3.4 Memory Controller Registers

The ARM.

Primecell SMC supports asynchronous page transfers. The following sections describe

the registers used to configure the ARM Primecell SMC for the supported modes of operation.

Table 3. PSRAM Refresh Control Register

A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Reserved

RegisterSelect

Reserved

PageMode

Temperature

Compensated

SelfRefresh

DPDMode

Reserved

Partial-Array

Self Refresh

0 0 0 0 0 0 0 0 0 0 0 0 0 (see text) 0 (see text)

Table 4. P-RCR: Temperature-Compensated Self Refresh Selections

A6 A5 Max. Case Temperature

1 1 850C

0 0 700C

0 1 450C

1 0 150C

Table 5. P-RCR: Partial-Array Self Refresh Selections

A2 A1 A0 Refreshed Memory array

0 0 0 Entire array (default)

0 0 1 Lower 3/4 of memory array

0 1 0 Lower 1/2 of memory array

0 1 1 Lower 1/4 of memory array

1 0 0 Zero

1 0 1 Upper 3/4 of memory array

1 1 0 Upper 1/2 of memory array

1 1 1 Upper 1/4 of memory array

Note: Configuration register names and field names may vary from that described in this

document, depending on the ASIC designer's final implementation.

3.4.1 Bank Registers

The SMC configuration and control signal timings are determined by programming the appropriate

registers for the particular memory bank(s) used. Each bank has its own set of registers. Table 6

shows the Chip Select bits for configuring the bank registers:

Table 6. Chip Select Configuration Register Bits (Sheet 1 of 2)

Bit Name Description

SMBIDCYRx[3:0] Idle Cycles (IDCY)

Bank Idle Cycle Control Registers 0 - 7

Read/Write idle or turnaround cycles in HCLK to prevent bus

contention on external memory data bus.

Turn around time = IDCY x tHCLK

0000 to 1111 (default)

SMBWST1Rx[4:0] Initial Wait States (WST1)

Bank Wait State 1 Control Registers 0 - 7

Number of wait states in HCLK for read access

Wait state time = WST1 x tHCLK

00000 to 11111 (default)

SMBWST2Rx[4:0] Page Wait States (WST2)

Bank Wait State 2 Control Registers 0 - 7

Number of wait states in HCLK for page read access after the

first read

Wait state time = WST2 x tHCLK

00000 to 11111 (default)

SMBWSTOENRx[3:0] Output Enable Delay (WSTOEN)

Bank Output Enable Assertion Delay Control Register 0 - 7

Output enable assertion delay from chip select assertion

0000 (default) to 1111

SMBWSTENRx[1:0] Write Enable Delay (WSTWEN)

Bank Write Enable Assertion Delay Control Register 0 - 7

Write enable assertion delay from chip select assertion

0000 (default) to 1111

SMBCRx[7:6] Memory Width (MW)

Bank Control Register 0 - 7

00 = 8-bit

01 = 16-bit

10 = 32-bit

11 = Reserved

Different default values for each memory bank

SMBCRx[5] Burst Mode ROM (BM)

Bank Control Register 0 - 7

0 = Non burst mode memory device (default)

1 = Burst ROM memory

SMBCRx[3] Chip Select Polarity (CSPol)

Bank Control Register 0 - 7

0= Active LOW SMCS (default)

1 = Active HIGH SMCS

For L18 SCSP CSPol = 0

AP-801

Application Note 15

See the ARM.

Primecell Static Memory Controller (PL092) Technical Reference Manual for

complete details regarding all of the Bank Registers.

4.0 Bus Interface Timing

All bus interface timing shown in the following diagrams are based on an HCLK of 100 MHz.

Timing symbols starting with R (e.g., R10) and W (e.g., W15) pertain to flash memory timing;

t (e.g., tRC) refers to the PSRAM timing. SMC register field names and values are shown in the

diagrams where they affect the SMC interface signal behavior.

4.1 Asynchronous Single Reads

On reset, the SMC and L18 SCSP default to Asynchronous Read mode, whereby reading from the

flash die returns array data.

7 Figure 4, "Flash Asynchronous Single-Word Read" on page 16 shows an asynchronous single

read from the flash die

7 Figure 5, "PSRAM Asynchronous Single-Word Read" on page 16 shows an asynchronous

single read from the PSRAM die.

HCLK is shown for reference only and is not used by the flash or PSRAM for asynchronous

transfers.

Note: On power up or after a reset, R5 must be satisfied for the flash die; tPU must be satisfied for the

PSRAM die. Also, the WAIT output from either die is invalid during asynchronous reads, and can

be ignored by clearing the WaitEn bit in the SMBCRx register.

SMBCRx[2] Wait Enable (WaitEn)

Bank Control Register 0 - 7

0 = PrimeCell SMC not controlled by external WAIT signal

(default)

1 = PrimeCell SMC looks for external WAIT signal

For L18 SCSP WaitEn = 0

SMBCRx[1] Wait Polarity (WaitPol)

Bank Control Register 0 - 7

0 = SMWAIT signal is active LOW (default)

1 = SMWAIT signal is active HIGH

For L18 SCSP WaitPol = 0

SMBCRx[0] Read Byte Lane Enable (RBLE)

Bank Control Register 0 - 7

0 = nSMBLS[3:0] all deasserted HIGH during system reads

(default)

1 = nSMBLS[3:0] all asserted LOW during system reads

For L18 SCSP RBLE = 0

Table 6. Chip Select Configuration Register Bits (Sheet 2 of 2)

Bit Name Description

AP-801

16 Application Note

Figure 4. Flash Asynchronous Single-Word Read

Figure 5. PSRAM Asynchronous Single-Word Read

(High-Z)

R8

R9

R3

R4

R5

R10R7

R13R12

WSTRD = 4

WSTOEN = 3

R1

R2

R1

Note: WAIT shown configured for low-true.

HCLK

SMADDR[24:1]

SMCS

SMOEN

SMWEN

WAIT

SMDATA[15:0]

F-RST#

(High-Z)

tOH

tCO

tOE

tOLZ

tPU

tBA

tOHZ

WST1 = 4

WSTOEN = 3

tHZ

tRC

tAA

tRC

HCLK

SMADDR[24:1]

SMCS

SMOEN

SMWEN

SMBLS

SMDATA[15:0]

P-VCC

AP-801

Application Note 17

4.2 Asynchronous Page Mode Reads

During Asynchronous Page mode reads, data is copied into a high-speed page buffer during the

initial access delay. Subsequent accesses output data from the page buffer when the lower address

bits are toggled. If any of the higher-order address bits are toggled, another initial access occurs and

the page-buffer is re-loaded starting from the new initial address.

The flash die in L18 SCSP has a page-buffer size of four words (64 bits); the PSRAM die has a

page-buffer size of sixteen words (256 bits). Since the SMC supports a maximum of four

consecutive words, the lower address bits, ADD[2:1] for the flash die and the PSRAM die, are used

to address data in the page buffer.

Figure 6 and Figure 7 show an Asynchronous Page mode read access from the flash and PSRAM

die respectively. HCLK is shown for reference purposes only and is not used by the either die for

Asynchronous Page mode transfers. The WAIT output from either die is invalid during

asynchronous reads, and can be ignored by clearing the WaitEn bit in the SMBCRx register.

Note: Because of the sharing of WST2 between write transfers and page read transfers, it is possible to

have only one setting at a time -- either the write delay or the page read delay. This means that:

7 For a write transfer, WST2 must be programmed with the write delay value.

7 For a page read transfer, WST2 must be programmed with the page access delay value.

Figure 6. Flash Asynchronous Page Mode Reads

00 01 10 11

(High-Z)

R9

R8

R108

R108

R108R3

R10R10R10R10R7

R13R12

WST2 = 1WST2 = 1

WST2 = 1WST2 = 1

WST2 = 1WST2 = 1

WST1 = 4

R4WSTOEN = 3

R1

R2

R1

Note: WAIT shown configured for low-true.

HCLK

SMADDR[24:3]

SMADDR[2:1]

SMCS

SMOEN

SMWEN

SMWAIT

SMDATA[15:0]

AP-801

18 Application Note

4.3 Asynchronous Writes

The memory dies of the L18 SCSP support asynchronous single-word writes. Figure 8 and Figure 9

show the asynchronous-write bus timing for the flash and PSRAM dies, respectively.

7 For the flash die, W1 and W10 must be satisfied for successful writes to the flash memory.

7 For the PSRAM die, the clock input must be held low, and tCW, tAW, and tWP must be

satisfied.

Figure 7. PSRAM Asynchronous Page Mode Reads

00 01 10 11

(High-Z)

1 2 3 4

tOH

tPAA

tOHtOH

tPAA

tOHtOE

tCO

tOLZ

tLZ

tBLZtBLZ

tOHZ

WST2 = 1WST2 = 1

WST2 = 1WST2 = 1WST2 = 1WST2 = 1

WSTOEN = 3

tCSL

tHZ

tCSL

WST1 = 4

tPCtPCtRC

tAA

HCLK

SMADDR[24:3]

SMADDR[2:1]

SMCS

SMOEN

SMWEN

SMBLS

SMDATA[15:0]

AP-801

Application Note 19

Figure 8. Flash Asynchronous Single-Word Write

Figure 9. PSRAM Asynchronous Single-Word Write

W10

W1

R13R12

W7W4

W3

WST2 = 2WSTWEN = 0

W3

W6

W8W5

Note: HCLK shown for reference only. WAIT shown configured for low-true.

HCLK

SMADDR[24:1]

SMCS

SMOEN

SMWEN

SMDATA[15:0]

SMWAIT

RST#

VPP

tDH

tDS

tBH

tBW

tWP

tAW

WST2 = 3

tWP

WSTWEN = 0WSTWEN = 0

tCHtAS

tCW

tWCtWC

HCLK

SMADDR[24:1]

SMCS

SMOEN

SMWEN

SMBLS

SMDATA[15:0]

AP-801

20 Application Note

4.4 Write Buffer Programming

The flash die of L18 SCSP features a 32-word Write Buffer enabling optimum programming

performance. To perform Write Buffer programming, data is written to an internal buffer, up to the

buffer's maximum size. The buffer data is then written to the flash memory array in buffer-size

increments. This improves system programming performance significantly over non-buffered,

single-word programming.

To use Write Buffer programming:

1. First issue the Write Buffer Setup command (0xE8) at the desired block's address; see Figure

10, "Write Buffer Bus Sequence" on page 20. This is followed by reading data bit D7 to

determine Write Buffer availability. If D7 = 1, the Write Buffer is available for loading data.

2. Next, issue a word count (minus 1) at the desired block's address. The allowable word count

range is 0x00 to 0x1F (ex: 0x00 = 1, 0x1F = 32). Follow this with the first data to be

programmed at the data start address. Subsequent writes to the die provide data and addresses,

up to the count limit. All subsequent addresses should be greater than the start address, but less

than . Also, data addresses must fall within the same erase-block

space, otherwise the write buffer sequence will abort.

3. Once the last data is written to the Write Buffer, issue the Confirm command (0xD0) at the

block address. This instructs the internal Write State Machine (WSM) to begin writing the

Write Buffer's contents to the flash memory array.

The flash die programs many flash cells in parallel, hence maximizing the flash programming

performance. Optimal performance is realized when programming is buffer-size aligned.

Additional buffer writes can be initiated by issuing another Write Buffer Setup command and

repeating the write-to-buffer sequence.

If errors occur, the device stops writing to the array and the Status Register indicates the type of

error. After checking the Status Register, clear it using the Clear Status Register command, 0x50. If

an attempt is made to program past a block boundary, the device will abort the operation.

Additional details regarding the Write Buffer feature of L18 SCSP flash memory can be found in

the Intel StrataFlash. Wireless Memory (L18 SCSP) datasheet and application note, AP-663 Using

the Intel StrataFlash. Memory Write Buffer.

Figure 10. Write Buffer Bus Sequence

Setup Cmd Check D7 Word Count Load Buffer Confirm Cmd

WA WA WA WA WA+Count WA

0xE8 0x80 Count First Data Last Data 0xD0

WA = Word Address w ithin the block to be programmed

Count = number of w ords to be w ritten - 1

SMADDR[24:1]

nSMCSx

nSMOEN

nSMWEN

SMDATA[15:0]

VPP

AP-801

Application Note 21

4.5 Concurrent Write Buffer Operations

As densities increase, alternative methods are needed to reduce the time it takes to program and

erase high-density, multiple flash memory. Program/erase throughput performance can be

improved by taking advantage of the built-in automation of Intel flash memory to concurrently

program and/or erase multiple flash devices.

Concurrent programming and erasing is described in the application note, AP-786 Concurrent

Program and Erase Using the Intel StrataFlash. Wireless Memory System (LV18/LV30). This

application note describes concurrent Single-Word-, Factory-, Buffered-, and Buffered Enhanced

Factory Programming (Buffered EFP), and erase operations; see Appendix A, "Additional

Information".

5.0 Summary

Intel StrataFlash. Wireless Memory (L18 SCSP) provides high performance flash and PSRAM

Asynchronous Page or Synchronous Burst mode reads, plus Synchronous Write mode for the

PSRAM. The Asynchronous Page Read mode and Synchronous Burst Read mode features

provides high data transfer rates for memory sub-systems while providing support for various I/O

voltages through the use of a separate I/O voltage supply pin, VCCQ.

The flexible interface of L18 SCSP provides the system designer with a simple, and most-often

"glueless" interface. This can reduce power consumption and material costs while increasing

overall system reliability and performance by eliminating the need for additional interface

components.

Intel StrataFlash. Wireless Memory (L18 SCSP) comes in a QUAD+ SCSP package for space-

constrained, high-density, high-performance memory systems. It is an excellent option for both

code execution and data storage applications requiring high density, high performance, and low

cost.

AP-801

22 Application Note

Appendix A Additional Information

Notes:

1. Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Visit the Intel World Wide Web home page at http://www.Intel.com for technical documentation and

tools.

3. For the most current information on Intel flash products, see http://developer.intel.com/design/flash/.

Document/Order

Number

Document Title

Call

Intel StrataFlash.

Wireless Memory System (L18 SCSP) 256-Mbit L18 with 64-Mbit

Synchronous PSRAM datasheet

253856

AP-786 Concurrent Program and Erase Using the Intel StrataFlash.

Wireless Memory

System (LV18/LV30)

292221 AP-663 Using the Intel StrataFlash.

Memory Write Buffer

297859 AP-677 Intel StrataFlash.

Memory Technology

292204 AP-646 Common Flash Interface (CFI) and Command Sets

292172 AP-617 Additional Flash Data Protection Using VPP, RP#, and WP#

ARM DDI 0203F ARM.

PrimecellTM

Static Memory Controller (PL092) TRM, Rev. r1p3





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