Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Memory/Storage
 
 
Memory/Storage  

Intel StrataFlash memory (J3) to Intel PXA270 applications processor design guide

Posted: 22 Nov 2004     Print Version  Bookmark and Share

Keywords:Embedded 

Intel StrataFlash memory (J3) to Intel PXA270 applications processor design guide

PDF document

Intel StrataFlash.

Memory (J3) to

Intel.

PXA270 Applications

Processor Design Guide

Application Note 769

June 2004

Order Number: 301901-001

2 301901

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright ) 2004, Intel Corporation

*Other brands and names may be claimed as the property of others.

301901 3

AP-769

Contents

1.0 Introduction ..................................................................................................................5

1.1 Intel StrataFlash. Memory (J3) ............................................................................5

1.2 Intel. PXA270 Applications Processor .................................................................5

2.0 Hardware Interfaces..................................................................................................6

2.1 Flash Memory Interface.........................................................................................6

2.2 PXA270 Memory Interface ....................................................................................6

3.0 Interface Considerations.........................................................................................8

3.1 Hardware Connections..........................................................................................8

4.0 Register Settings........................................................................................................9

4.1 Flash Memory Register Settings ...........................................................................9

4.2 Processor Register Settings................................................................................10

4.2.1 Core Clock Configuration Register (CCCR) ...........................................10

4.2.2 Static Memory Control Registers (MSC[2:0]) .........................................10

5.0 Bus Operation and Timings.................................................................................11

5.1 Asynchronous Single Reads ...............................................................................11

5.2 Asynchronous Page-Mode Reads.......................................................................12

5.3 Asynchronous Writes ..........................................................................................13

5.4 Write-to-Buffer Programming ..............................................................................13

6.0 Summary......................................................................................................................14

Appendix AAdditional Information...........................................................................................15

4 301901

AP-769

Revision History

Date of

Revision

Revision Description

06/13/04 -001 Original version

AP-769

301901 5

1.0 Introduction

This application note covers interfacing Intel StrataFlash.

Memory (J3) to Intel.

PXA270

Applications Processor. It discusses general concepts involved when interfacing to the integrated

features and control signals of Intel StrataFlash.

Memory (J3).

This document was written based on information available at the time on Intel StrataFlash.

Memory (J3) and Intel .

PXA270 Applications Processor. Any specifications changes to either

device since the time of writing may not be reflected in this document. Refer to the appropriate

documents or sales personnel for the most current information before finalizing any design. See

Appendix A, "Additional Information".

1.1 Intel StrataFlash.

Memory (J3)

Intel StrataFlash.

Memory (J3) provides the following features:

7 Combines high performance page-mode reads, buffered writes, and flexible block locking

with reliable and proven multi-level-cell (MLC) technology

7 Available in 32-, 64-, 128-Mbit, and 256-Mbit densities, the devices offer more density in less

space, support for code and data, and easy migration to future devices.

7 Ideal for mainstream applications requiring large storage space for code and data. For

example, networking, telecommunications, digital set-top boxes, digital audio recording, and

digital imaging.

1.2 Intel.

PXA270 Applications Processor

The PXA270 Applications Processor is an integrated system-on-a-chip microprocessor for high

performance, low power portable devices and provides the following features:

7 Incorporates the Intel.

XScaleTM

microarchitecture with on-the-fly voltage and frequency

scaling, and sophisticated power management to provide industry-leading MIPS/mW

performance. Intel XScale is a 32-bit RISC micro-architecture that is ARM* architecture

compliant.

7 Powerful multimedia coprocessor that supports Intel MMXTM

integer instructions to accelerate

audio and video processing.

7 Contains a 32-KByte instruction cache and a 32-KByte data cache, using a 256-bit line-fill

buffer. The on-chip memory controller is based on a Unified Memory Architecture wherein all

external memory devices share a common address and data bus, and the external memory

space is viewed as a linear collection of bytes numbered upwards from 0.

The memory controller consists of four main control units for interfacing with synchronous

dynamic memory (SDRAM), static memory (SRAM; includes ROM and Flash memory),

PCMCIA, and companion chips.

7 The static memory space supports Intel.

flash memory in asynchronous 4- or 8-word page-

read modes, and synchronous 8- or 16-word burst-read modes.

7 Bus widths of 16- and 32-bits are supported, with maximum addressability of 64 Mbytes per

chip select.

AP-769

6 301901

7 External memory clock rates from 13 MHZ to 104 MHz at typical I/O voltages of 1.8 V, 2.5 V,

3.0 V, and 3.3 V.

2.0 Hardware Interfaces

This section describes the hardware interface signals between Intel StrataFlash.

Memory (J3) and

the Intel .

PXA270 Applications Processor. This document assumes that all other device signals

and power supplies are connected to ensure proper device operation.

2.1 Flash Memory Interface

The following signals provide a hardware interface to the Intel StrataFlash.

Memory (J3) device:

2.2 PXA270 Memory Interface

Intel .

PXA270 Applications Processor memory interface supports various memory types. Its

external memory bus supports SDRAM, page and burst mode flash memory, synchronous masked

ROM (SMROM), page-mode ROM, SRAM, Variable Latency I/O (VLIO) memory, PC card

expansion memory, and compact flash. See Figure 1. These memory types are programmable

through the PXA270 Applications Processor memory controller configuration registers.

A[AMAX:1]

ADDRESS: Device address inputs. A1 is the least significant word (x16) address line; A0

is not used in x16 mode (BYTE# = VIH). AMAX = A21 (32 Mb), A22 (64 Mb), or A23 (128

Mb).

D[15:0]

DATA I/O: Outputs during read operations or inputs during write operations. D[15:0] are

High-Z (float) whenever CE# or OE# is deasserted.

RP#

RESET: Low-true input. RP#-low resets internal automation and inhibits write operations.

RP#-high enables normal operation.

CE#

CHIP ENABLE: Low-true input. CE#-low enables the device. CE#-high disables the

device placing it in standby mode. CE#-high places D[15:0] at High-Z.

OE#

OUTPUT ENABLE: Low-true input. OE#-low enables the output buffers. OE#-high

disables the output buffers and places D[15:0] at High-Z.

WE#

WRITE ENABLE: Low-true input. WE#-low enables the input buffers. Address and data

are latched on the rising edge of WE#. WE#-high disables the input buffers.

BYTE#

BYTE ENABLE: Low-true input. BYTE#-low places the device in x8 mode. Data is input

or output on D[7:0] while D[15:8] float. Address A0 is the byte address bit. BYTE#-high

places the device in x16 mode and turns off the A0 input buffer. Address A1 then becomes

the lowest-order address bit.

VPEN

PROGRAM/ERASE ENABLE: Input. The voltage applied to VPEN must be greater than

VPENLK in order to program or erase array blocks or to configure block lock bits.

AP-769

301901 7

Intel .

PXA270 Applications Processor uses the following external memory interface signals:

Figure 1. Intel .

PXA270 Memory Interface Configuration

SDRAM Partition 3

SDRAM Memory

Interface

Up to four partitions of

SDRAM memory

(16 or 32 bits wide)

nSDCS3

SDRAM Partition 2

SDRAM Partition 1

SDRAM Partition 0

nSDCS2

nSDCS1

nSDCS0

SDCLK2, SDCKE1

SDCLK1, SDCKE1

Static Bank 0

("Bootable" Memory)

Static Bank 1

Static Bank 2

Static Bank 3

nCS0

nCS1

nCS2

nCS3

RDY

SDCLK0

Static Bank 4

Static Bank 5

nCS4

nCS5

Static Memory or

Variable Latency

I/O Interface

Up to six banks of ROM,

Flash, SRAM, Variable

Latency I/O

(16 or 32 bits wide)

Synchronous

Static Memory

Interface

Up to four banks of

synchronous static

memory (nCS[3:0])

(16 or 32 bits wide)

Buffers and

Transceivers

MA[25:0]

MD[31:0]

DQM[3:0]

nSDRAS, nSDCAS, nWE, nOE

Card Control

Card Memory

Interface

Up to two sockets

supported (requires some

external buffering)

Memory

Controller

Alternate Bus

Master

MBREQ

MBGNT

RDnWR

MA[25:0]

Memory Address Bus. The memory address bus transfers address information between

the processor and external memory.

MD[31:0]

Memory Data Bus. The memory data bus carries data between the processor and

external memory.

AP-769

8 301901

3.0 Interface Considerations

This design example uses two 28F640J3 flash memory devices connected directly to the PXA270

Applications Processor on a 32-bit wide data bus. Special considerations must be taken into

account when connecting two flash devices together such that simultaneous commands must be

written to the upper (MD[31:16]) and lower (MD[15:0]) portion of the data bus. This ensures that

both devices are issued the same command sequences.

It is assumed that the flash memory is located in the boot space of the Intel .

PXA270 Applications

Processor. When the PXA270 comes out of reset, it begins fetching and executing instructions at

address 0x0000, which corresponds to nCS0.

The interface timings reflect a memory controller clock (CLK_MEM) frequency of 104MHz.

Other bus speeds and memory sizes can be substituted by changing the appropriate processor

register settings. This is described in the following sections.

This sample interface design does not include all information regarding system initialization,

interrupt control, exception handling, or other peripheral device operations. External device

signals/pins should be asserted or negated as necessary for desired device operation. Also, proper

power supply voltages must be applied in accordance with the latest datasheet information. Be sure

to read all applicable documentation (e.g., datasheets, user manuals, and specification updates)

before attempting this interface.

Note: This application note covers processor register settings specifically for using the 28F640J3.

Register settings and timings may be different for other density Intel StrataFlash.

memory devices.

See the latest datasheet for specific information.

3.1 Hardware Connections

Figure 2, "PXA270 Applications Processor and 28F640J3 Hardware Connections" on page 9

shows the hardware connections between the 28F640J3 flash memory and the Intel .

PXA270

Applications Processor. This design example uses Chip Select nCS0; however, you can use any of

the other static memory Chip Selects instead by configuring the appropriate Chip Select registers.

Also note that only nCS[3:0] support synchronous-burst reads.

At start-up (reset), the PXA270 Applications Processor samples the BOOT_SEL[0] input pin to

determine the bus width of the boot memory. BOOTSEL[0] is shown configured for 32-bit bus

width.

nCS[5:0]

Static Memory Chip Selects. Active-low output, the chip selects are individually

programmable through the memory configuration registers. nCS0 is initialized at reset for

boot-ROM selection.

nOE

Output Enable. Active-low output, nOE is asserted during memory reads to enable the

data bus drivers of the selected external memory device.

nWE

Write Enable. Active-low output, nWE is asserted during write operations to external

memory devices.

AP-769

301901 9

Note: This is the connection for 32-bit operation at boot-up.

RP# is shown connected to the System Reset signal. Alternately, RP# can be connected to the

nRESET_OUT signal. In this case, the 28F640J3 will not only be reset when nRESET is asserted,

but also for "soft" reset events such as sleep mode, watchdog reset, and GPIO reset (if enabled).

4.0 Register Settings

After a system reset, processor and memory controller registers must be programmed with

appropriate values to enable the processor to utilize the page-mode read feature of the 28F640J3.

The following sections describe the affected registers and their settings.

4.1 Flash Memory Register Settings

The default read mode of the 28F640J3 is asynchronous read array mode featuring a 4-word (16

byte) page buffer. There are no flash memory register settings necessary for the 28F640J3 to

function with the PXA270 Applications Processor.

Figure 2. PXA270 Applications Processor and 28F640J3 Hardware Connections

MD[15:0]

MA[23:2]

MD[31:0]

nCS0

nWE

nOE

nRESET

PXA270

Applications

Processor

MD[31:16]

System

Reset

28F640J3

Flash Memory

D[15:0]

CE0

OE#

WE#

RP#

A[22:1]

BOOT_SEL[0]

See

Note

28F640J3

Flash Memory

D[15:0]

CE0

OE#

WE#

RP#

A[22:1]

CE1

CE2

CE1

CE2

BYTE#

BYTE#

V CCQ

V CCQ

AP-769

10 301901

4.2 Processor Register Settings

Intel .

PXA270 Applications Processor contains registers for configuring the external memory

interface. The Core Clock Configuration Register (CCCR), SDRAM Refresh Control Register

(MDREFR), Synchronous Static Memory Control Register (SXCNFG), and Static Memory

Control Register (MSC[2:0]) settings are described in the following sections. Register bit fields

that affect memory interface operations with the 28F640J3 are discussed; all other bit fields should

be programmed as necessary to ensure proper device operation.

4.2.1 Core Clock Configuration Register (CCCR)

PXA270 Applications Processor contains a Clocks Manager to manage its multiple clock sources.

The Core Clock Configuration Register (CCCR) sets the memory controller clock (CLK_MEM)

frequency. For this design example, a clock multiplier setting of 8 (CCCR:L[4:0] = 0b01000) is

used to produce a CLK_MEM frequency of 104.00 MHz from a 13 MHz crystal oscillator source.

The `N' field of the CCCR should be programmed for desired core frequency operation.

4.2.2 Static Memory Control Registers (MSC[2:0])

MSC[2:0] are the control registers used to configure the static memory chip selects nCS[5:0] in

pairs for asynchronous memory accesses within each Static Memory Bank. Each MSCx register

contains two identical configuration fields, one for each of its corresponding Chip-Selects.

All register fields are specified in number of CLK_MEM cycles. If any of the nCS[3:0] static

memory banks is configured for synchronous static memory operation via SXCNFG:SXENx, the

corresponding half-word of MSC[1:0] is ignored. However, the data-width field, RBWx, within the

affected half-word is still used. Also, for non-SDRAM-like Synchronous Flash (SXCNFG:SXTPx

= 0b10), the MSCx:RDFx register values are still used for asynchronous write timings.

When asynchronous page-mode flash is used, the MSCx:RDFx and MSCx:RDNx fields configure

the delay timings for initial-access and page-access delays, respectively. The MSCx:RTx field

configures the type of memory used. The 28F640J3 only supports 4-word page-mode reads.

Programming MCS0[15:0] with 0x12C2 configures nCS0 for asynchronous page-mode reads with

the 28F640J3 as follows:

7 RBUFF0 (MSC0[15]) = 0b0 (Slower device - Return Data Buffer)

7 RRR0 (MSC0[14:12]) = 0b001 (Read recovery: 1 * 2 + 1 = 3 CLK_MEMs)

7 RDN0 (MSC0[11:8]) = 0b0010 (ROM delay - next access: 2 + 1 = 3 CLK_MEMs)

7 RDF0 (MSC0[7:4]) = 0b1100 (ROM delay - first access: 12 + 2 = 14 CLK_MEMs)

7 RBW0 (MSC0[3]) = 0b0 (data bus width: 32 bits)

7 RT0 (MSC0[2:0]) = 0b010 (memory type: burst-of-four flash w/ non-burst writes)

AP-769

301901 11

5.0 Bus Operation and Timings

For the following discussions, consult the appropriate PXA270 Applications Processor and

28F640J3 flash memory documents for specific timing information of the individual components

presented in this design example. Flash memory timings start with R (read) or W (write). PXA270

timings start with T, and register field names are shown where they affect the respective delays.

5.1 Asynchronous Single Reads

On power-up or reset, the PXA270 Applications Processor registers default to settings that enable

them to access the slowest ROM and flash memory available. In this example, the BOOT_SEL[0]

pin is tied low for 32-bit memory bus operation.See Figure 2, "PXA270 Applications Processor

and 28F640J3 Hardware Connections" on page 9. RDFx, RDNx, and RRRx default to the

maximum number of CLK_MEMs allowed.

The 28F640J3 defaults to asynchronous read-array mode at startup. Figure 3 shows the bus timing

for an initial asynchronous single read following a reset. Note that R5 must be satisfied before

reading from the flash memories.

Figure 3. Asynchronous Single-Word Read

R5

R10

R9R4

R7

tROMAH

R8

tROMAS

R3

RDF+1

R6

R2

RRR*2+1RRR*2+1RDF+2RDF+2

(CLK_MEM)

MA[23:2]

nCS0

nOE

nWE

MD[31:0]

RP#

AP-769

12 301901

5.2 Asynchronous Page-Mode Reads

The 28F640J3 defaults to read-array mode upon reset. When reading from the flash device, array

data is copied into a high-speed page buffer. The page-buffer size of the 28F640J3 is 4 words.

Intel .

PXA270 Applications Processor supports 4-word or 8-word page-mode; 4-word page-mode

is used with the 28F640A. The low-order memory address bits MA[3:2] control access to the flash

memory page-buffer data. No additional flash commands are necessary for asynchronous page-

mode operation.

Figure 4 shows the bus timing for burst-of-4 asynchronous page-mode array reads using the values

describe in Section 4.2, "Processor Register Settings" on page 10.

Figure 4. Asynchronous Page-Mode Reads

00 01 10 11

R15

R2

R4

R3

R10R10

R9R7

R8

tROMAHtROMAS

R6

RDF+1

RRR*2+1RRR*2+1

RDN+1RDN+1

RDF+2RDF+2

(CLK_MEM)

MA[23:4]

MA[3:2]

nCS0

nOE

nWE

MD[31:0]

AP-769

301901 13

5.3 Asynchronous Writes

The value programmed into MSCx:RDFx determines the number of CLK_MEM cycles for which

nWE (WE#) is asserted. In this design example, MSC0:RDF0 = 0xC, provides fifteen CLK_MEM

cycles (RDF+2) for initial accesses during page-mode reads. As a result, nWE is asserted for

thirteen CLK_MEM cycles, which satisfies the Write Pulse Width (W3) of the 28F640J3. Figure 5

shows the bus timing for an asynchronous write.

5.4 Write-to-Buffer Programming

Intel StrataFlash.

Memory (J3) features a 16-word (32-byte) Write Buffer that enables optimum

programming performance. For Write Buffer programming, data is written to the internal write

buffer, then written into the flash memory array in buffer-size increments. This can improve system

programming performance more than 20 times over single-word programming.

To use Write Buffer programming, perform the following:

1. First issue the Write-to-Buffer setup command, 0xE8, at the desired block's address. See

Figure 6, "Write-to-Buffer Bus Sequence" on page 14.

2. Read data bit D[7] to determine part readiness. If D[7] = 1, the Write Buffer is available for

loading.

3. Issue the word count at the desired block's address. The allowable word count range is 0x00 to

0x0F.

4. Write the first data to be programmed at the data start address. \

Subsequent writes provide data and addresses, up to the count limit. All subsequent addresses

must be greater than the start address but less than the start address + buffer size, otherwise,

the operation will abort. Also, data addresses must fall within the same erase-block space or

the operation will abort.

Figure 5. Asynchronous Writes

W7

tromDH

tromDS

W4

W9W9

W6W3

tromCEH

RDF+1

W2 W3

tromCES

tromASW

RDF+1

RRR*2+1

tromAH

RRR*2+1

tromAS

W8W5

(CLK_MEM)

MA[23:2]

nCS0

nOE

nWE

MD[31:0]

AP-769

14 301901

5. Once the last data is written to the Write Buffer, issue the Write Confirm command, 0xD0, at

the block's address. This instructs the internal Write State Machine (WSM) to begin writing

the Write Buffer's contents to the flash memory array.

The device programs many flash cells in parallel, thereby maximizing the programming

performance of the flash device. Optimal performance is realized when write buffer programming

is buffer-size aligned. Additional buffer writes can be initiated by issuing another Write Buffer

setup command, and repeating the write-to-buffer sequence.

If errors occur, the flash device stops writing to the array and the Status Register indicates the type

of error. After checking the Status Register, it should be cleared using the Clear Status Register

command, 0x50. If an attempt is made to program past a block boundary, the device will abort the

write-to-buffer operation.

For additional details regarding the Write to Buffer feature, see the 3 Volt Intel StrataFlash.

Memory datasheet.

6.0 Summary

Intel StrataFlash.

Memory (J3) provides 2X the bits in 1X the space by utilizing reliable multi-

level-cell (MLC) storage technology. A separate I/O voltage supply input, VCCQ, provides support

of different I/O voltages for additional functionality.

Intel StrataFlash.

Memory (J3) is available in a variety of packages and densities for increased

flexibility. It is an excellent option for both code and data applications where high density and low

cost is required.

The flexible interface of the Intel StrataFlash.

Memory (J3) gives the designer a simple "glueless"

interface with PXA270 helping to reduce power consumption, decrease cost and increase overall

system reliability by eliminating the need for additional interface components.

Figure 6. Write-to-Buffer Bus Sequence

Setup Cmd Word Count Check D7 Load Buffer Confirm Cmd

BA BA BA DA DA+Count BA

0xE8 Count 0x10 BD BD 0xD0

BA = Buff er Address

DA = Dev ice Address

Count = # of words to be written

BD = Buf f er Data

Address

nCS0

nRD

nWE

Data

VPEN

AP-769

301901 15

Appendix A Additional Information

Order Number Document/Tool

290667 Intel StrataFlash. Memory (J3) Datasheet

298130 Intel StrataFlash. Memory (J3) Specification Update

292286

AP-738 Reduce Manufacturing Costs with Intel. Flash Memory Enhanced Factory

Programming

Notes:

1. Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and

tools.

3. For the most current information on Intel flash products, see http://developer.intel.com/design/flash/.

AP-769

16 301901

Page Intentionally Left Blank





Comment on "Intel StrataFlash memory (J3) to Int..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top