Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Power/Alternative Energy
 
 
Power/Alternative Energy  

Design level-shifter with low power dissipation

Posted: 23 Dec 2015     Print Version  Bookmark and Share

Keywords:SoCs  level-shifters  inverters  dissipation  power consumption 

For the second inverter (M6-M7), gate of M7 is connected directly to IN_B. This ensures prompt transition of OUT from high-to-low when IN goes from high-to-low. Thus M4 gets ON quickly. With M3 already ON on account of fast transition of IN_B, the pull-up path (M2-M4) gets ON quickly thus ensuring fast transition of A from low-to-high. Since in this state, NMOS transistor M3 will be ON, voltage at C would not be VDDH, but lesser than VDDL by threshold (Vt) of NMOS. This would result in A being at (VDDL – Vt (M3)). This could become the potential source of static current consumption through second inverter (M6-M7). To eliminate this, transistor M5 has been added which pulls up node A to VDDH and hence eliminates the possibility of any static current flowing through second transistor (M6-M7).

However, as the difference between two power supplies (VDDH and VDDL) increases, the power consumption will also increase: The time taken by node A to come up will be increased, resulting in a direct current path through M6-M7 for a longer period of time, thus resulting in increased power consumption.

Since the proposed circuit doesn't include any transistor that is always ON (unlike the conventional circuit), there is no static current consumption.

Simulation results

Figure 4: Comparison of steady-state current in conventional and proposed circuit.

Figure 5: Input (Red) and Output (blue) waveforms of the proposed circuit.

Figure 5: Input (Red) and Output (blue) waveforms of the proposed circuit.

Conclusions
The proposed circuit provides an immense reduction in steady-state current for IN=1. For IN=0, steady-state current is slightly lower. Hence, the proposed circuit results in low power dissipation (particularly static power dissipation) by eliminating the always ON element present in the conventional design.

References
1. US6429683, Miller et al., "Low-power CMOS digital voltage level shifter", August 6, 2002.
2. "Level Shifter Design for Low Power Applications", International Journal of Computer Science & Information Technology, 10/2010;

About the authors
Kaushalendra Trivedi, Luv Pandey, Ramji Gupta and Gaurav Agrawal contributed this article.


 First Page Previous Page 1 • 2



Comment on "Design level-shifter with low power ..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top