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CoolCube 3D interconnect supports FinFET manufacturing

Posted: 05 Aug 2015     Print Version  Bookmark and Share

Keywords:CEA-Leti  FinFET  3D interconnect  silicon-on-insulator  FDSOI 

CEA-Leti has revealed that its CoolCube 3D interconnect technology is ideal for FinFET manufacturing processes as well as with fully-depleted silicon-on-insulator (FDSOI) manufacturing processes. The research laboratory showcased the feasibility of CoolCube used to stack FinFET layers on its 300mm production line.

This is particularly relevant to Qualcomm that has previously announced that it would be using a monolithic 3D (M3D) approach to stacking circuits instead of through-silicon vias (TSVs). CEA-Leti's previous work on CoolCube had been based only on FDSOI.

CoolCube 3D interconnect

CoolCube is Leti's sequential integration technology that stacks of active layers of transistors. It is enabled by halving the thermal budget for manufacturing transistors in second and higher layers while minimising a sacrifice in performance. It also allows about 10,000 times higher density of interconnect than is possible with TSVs.

For CoolCube the next layer is produced on a second wafer and then transferred as a thin silicon wafer film peeled off from a wafer blank after planarisation. Because the transferred film is so thin and optically transparent, well under a micron (compared to around 50µm thin for thinned wafers), the layer of transistors that are processed on top can be aligned to the bottom transistors with lithographic precision.

The process is good for stacked ICs as well as for the combination of heterogeneous process layers and the co-integration of sensors, MEMS with CMOS. "In heterogeneous integration, we expect CoolCube to be an actual enabler of smart-sensor arrays by allowing a close integration of sensors, detection electronics and digital signal processing," said Maud Vinet, Leti's advanced CMOS laboratory manager. "In the digital area, we expect this 3D technique to allow a gain of 50 per cent in area and 30 per cent in speed compared to the same technology generation in classic 2D, gains comparable to those expected in the next generation," she also said.

The researchers reckon that the co-integration of two layers of 14nm technology could create a denser FPGA than a 2D design in 10nm process technology. However that would require a fine-grained redistribution of the design so that memory would be substantially contained in one layer and logic substantially in another.

That requires supporting EDA software tools. "We are working with Mentor Graphics and a couple of other EDA firms on that," said Vinet.

The next steps will include: 1) Getting EDA firms to deliver tools to support 3D design with CoolCube; 2) Scaling up production from small test circuits to commercial scale circuits; and 3) Working on customer design, said Vinet. "The target is to intersect the 10nm process node late in 2017 early in 2018," she added.

- Peter Clarke
  EE Times Europe





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