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Understanding parasitic extraction of FinFETs

Posted: 15 Jun 2015     Print Version  Bookmark and Share

Keywords:FinFETs  Memory  parasitics  Parasitic resistance  CPU 

The introduction of FinFETs at 16 and 14 nm nodes paved the way for higher density and performance, and reduced power usage, but it also increases challenges in design and validation. Memory designers need a tool that can help them analyse parasitics quickly and accurately throughout the design cycle.

Introduction to FinFETs
FinFETs are three dimensional structures that rise above the substrate and look like a fin, hence the name. Theses fins form the source and the drain, and the gate wraps around the source and drain, providing better control of the channel.

When the device is in the off state, there is very little leakage current. With FinFET designs, there is low threshold voltage, and a lower supply voltage can be used. This drop in supply voltage results in reduced power usage while maintaining performance.

Parasitic resistance and capacitance of FinFETs
With FinFET structures, it is important to accurately capture the parasitic resistance and capacitance within the device, as well as inter-device interactions. Also, some foundries model floating devices in between the designed FinFETs, and it is important to capture the coupling to the floating devices, as well as coupling between the main designed devices.

Figure 1: When extracting FinFETs, it is important to capture the coupling to floating devices, as well as coupling between the main designed devices.

Parasitic resistance is also important. As the fin channel and the source drain regions narrow, increased source drain resistance degrades the performance of the devices. The source/drain resistance is composed of spreading, sheet and contact resistance, and is around 150Ω for p-type FinFETs, and 116Ω for n-type FinFETs, with gate overdrive voltage between 0.6 and 1.2V [1].

The parasitic capacitance and resistance within and between FinFETs can be modelled either by the parasitic extraction tool, or in the device model used for simulation. It is important to ensure that there is no double counting of effects, and no missing effects, in the boundary between extraction tool and device model. The trend for smaller nodes is to have the parasitic tool do more of the modelling, since it can take the layout-dependent effects into consideration.

Flat vs. hierarchical extraction
When doing parasitic extraction with FinFETs, flat extraction is often done since it allows all coupling effects to be taken into consideration. But sometimes, the runtime of a flat extraction can be too long. Hierarchical extraction can be done to reduce runtime. In hierarchical extraction, each level of the hierarchy is extracted in isolation, and then each level of hierarchy is stitched together. The upper levels of hierarchy can see coupling capacitance effects into lower levels of hierarchy, but then the coupling is grounded. This is called a "grey box" flow.

Boundary condition extraction
An alternate approach is to apply boundary conditions on a single cell. Extraction using boundary conditions enables the extraction of an isolated cell by simulating the parasitic effects of neighbouring conductors, either by reflecting the boundaries, or by virtually placing the same block repeatedly. The illustration below shows an example with both reflective and periodic boundaries. A reflective boundary is equivalent to placing a reflective wall at the boundary, and placing a mirror image of the cell on the other side of the wall. A periodic boundary replicates the enclosed geometries, creating copies on the other side of the boundary. The upper left corner of the figure shows a cell extracted in isolation, where the y direction is periodic, and the x direction is reflective. The larger diagram on the right shows an entire array of cells as a flat extraction. Extracting just a single cell, but reflecting the boundaries can provide almost the same accuracy as running a flat extraction, with significant runtime advantages. This boundary condition methodology works well for memories, because identical structures are repeated over and over again.

Figure 2: A boundary condition extraction technique works well for memories, because identical structures are repeated over and over again.

Using a field solver for extraction of memory designs
For memory designs, the bit cell is usually defined first, and it can be extracted and simulated in isolation. Then, boundary condition extraction can be used to determine how the neighbourhood will affect the performance of the bit cell. In the extraction process for memories, every stage of design verification can benefit from field solver accuracy.

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