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Extraction issues in advanced nanometre IC design

Posted: 09 Jun 2015     Print Version  Bookmark and Share

Keywords:FinFET transistors  simulation  double patterning  extraction  EDA 

For designs that require many extraction corners, the new platform performs simultaneous multi-corner extraction with about a 15-20% runtime increase for each additional corner, and no loss in accuracy. Because it uses a deterministic technique, single corner and multi-corner runs deliver the same results, which is not always the case for Monte Carlo approaches.

Selective net processing and netlist reduction
Another way to speed up turnaround time and also reduce the volume of data to manage is a technique called selective net processing. This enables designers to tailor the amount of data generated for simulation by selecting the specific parasitic model they want for each net. Designers can select distributed RCC (with coupling capacitance), RC (no coupling capacitance), C, or R on a net-by-net basis. They can also control extraction by layer. For example, to reduce simulation time while taking into account the parasitic effects for large power and ground nets, designers can extract VDD and VSS nets including only via resistance, and excluding metal layer resistance. This is useful because vias contribute the most resistance to the power/ground net. This enables faster simulation while still maintaining the required design margins.

Figure 3: Calibre xACT has selective processing capabilities. In this example, a netlist is generated with different net models for different types of nets. For power (VDD) and ground (VSS) nets, only via resistance is extracted into the netlist. The critical differential pair nets PLUS and MINUS are extracted in RCC mode, and all of the other nets will only contain total capacitance values.

Another time-saving approach is to generate multiple netlists from a single parasitic extraction database (or extraction run). This can be used to generate multiple netlist formats as well as netlists with multiple parasitic models, which can be controlled on a per-net basis. This saves time because extraction doesn't have to be run every time a different netlist needs to be generated, and enables multiple post-layout analyses from a single extraction run. For example, a designer can perform a single RCC extraction run on all nets in the design, and then generate a SPICE netlist with RCC net models for all signal nets to do a timing analysis, followed by a resistance-only netlist in DSPF format for electromigration analysis.

Simulator performance is highly dependent on the size of the netlist, and parasitic elements can increase netlist size by orders of magnitude. More accuracy means more parasitics, but the circuit becomes more difficult and lengthy to analyse. That's why flexible netlist reduction techniques are important to minimise the amount of parasitic data generated for post-layout simulation to just what is needed (figure 4). This speeds up simulation performance and reduces analysis time and convergence problems.

Figure 4: Designers can fine tune netlist reduction settings to control the level of accuracy and netlist size as needed. In this example, the via array is reduced to a much smaller size, enabling faster simulation while retaining accuracy.

EDA vendors stepping up
Digital, custom, analogue or RF design teams working at any node, but particularly at 16 nm and below, require an extraction tool that is faster, more accurate, and more flexible than previous generations of can provide. EDA vendors are stepping up to the challenge with new extraction tools built on more advanced architectures and algorithms to deliver the needed capabilities.

About the author
Casey Robertson is a director of product marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS, and extraction products. He has been with Mentor Graphics for 15 years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley.


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