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Altera details latest tech powering the Quartus II FPGA tool

Posted: 13 May 2015     Print Version  Bookmark and Share

Keywords:Altera  FPGA  OpenCL  processor 

Throughout the years, Altera has continuously brought to market successive line-ups of FPGA that boast increased capacity and performance, e.g., Stratix, Stratix II, Stratix III, Stratix IV, Arria V and Stratix V devices. Nonetheless, there has been a remarkable and discontinuous jump in capabilities as a result of new architectural features and technology node associated with the next-generation Arria 10 and Stratix 10 families.

Altera FPGA capabilities

In order to accommodate these increased device capabilities, Altera has unveiled its latest technology at the heart of its Quartus II FPGA development environment, the Spectra-Q engine. Coupled with a truly hierarchical database, the Spectra-Q engine supports a fine-grained approach in which the user can start/stop at each compilation stage, with the system supporting re-entry and incremental optimisation at each stage. For example, the user can first use the periphery placer to establish and lock down those portions of the device that communicate with the outside world, and then move on to the core placer, and then the router.

FPGA hierarchical database

According to the company, one extremely powerful aspect of all this is the use of BluePrint Platform Designer that provides the ability to drag-and-drop peripheral IP functions such as traffic managers and Interlaken interfaces, with the system automatically ensuring legal placements and use of available resources.

FPGA design platform

The hierarchal design flow facilitates IP reuse and supports selective IP recompile, which means that updating an IP block no longer requires the recompilation of the entire database.

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