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Qualcomm's 3D SoCs to be built on single layered die

Posted: 07 Apr 2015     Print Version  Bookmark and Share

Keywords:3D  SoCs  VLSI  TSVs  Qualcomm 

Qualcomm is creating two basic types of 3DV interconnection methods with the hope of deploying them by 2016. These new types of 3D interconnection comes in two flavours face-to-back (F2B) and face-to-face (F2F).

F2B is easier because it doesn't need precision bonding but instead just puts a thin layer of silicon on top of the finished first layer and starts building the second layer using traditional vias. Unfortunately, the bottom layer was likely produced using temperatures as high as 1,200°C.

Fabrication process

In the fabrication process of front-to-back (F2B) 3DVs (a) the bottom tier is created the same way as 2D-ICs. (b,c,d) To add another layer, first a thin layer of silicon is deposited on top of the bottom tier. (e) This front-end-of-line (FEOL) process of the top tier permits the addition of normal vertical vias and top-tier contacts. (f) Finally back-end-of-line (BEOL) processing creates the top-tier. (Source:Qualcomm)

The next layer, however, will have to limit temperatures in order to keep from liquidating layer one's copper interconnects, which have a melting point of 1,085°C. To solve, Qualcomm could use tungsten as interconnects on layers one, which are slightly slower, but have a melting point of 5,930°C. A second solution would be to limit the temperatures on the top level, to say 625°C, which would lessen the performance of the second layer transistors by 27.8 per cent for PMOS and 16.2 per cent for NMOS. Thus the ideal 3D chip is unachievable today using F2B, overall sacrificing about 37 per cent in performance and 41 per cent in power.

F2F, on the other hand, allows both chips to use copper interconnects and optimally performing transistors, but has the disadvantage, according to Arabi, that the F2F method requires larger vias the size of which are limited by the accuracy with which the two facing wafers can be bonded. Qualcomm, however, believes that by using a mix of the two techniques it will be able to produce fully optimised 3DV SoCs with an unlimited number of layers. In fact, with appropriate partitioning and floor planning, Arabi believes 3DV chips can be produced that are faster, smaller, consume less power and operate at lower temperatures than putting the same functions on a single 2D chip.

Fabrication process

In the fabrication process of front-to-front (FF) 3DVs requires wafer-level bonding and hence the vias can only be a small as the accuracy of the bonding method. (Source: Qualcomm)

The final advantage of 3DV chips, according to Arabi, is that you only need to use the most expensive and latest node technology on the bottom layer. For instance, the bottom layer housing the CPU, GPU and other high-speed devices can be fabricated at 10-to-14 nanometer, whereas the higher layers housing less critical functions can be fabricated at a less expensive relaxed node of, say, 28-nanometers. He also predicted that the best yielding SoCs will only use two layers, whereas three layers will likely only be used for customers who also want to integrate radio frequency (RF) functions on the top layer.

- R. Colin Johnson
  EE Times


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