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Advanced fault models in small-scale CMOS tech nodes

Posted: 05 Feb 2015     Print Version  Bookmark and Share

Keywords:CMOS  defects  Single Stuck-at  Transition Fault  ATPG tool 

Small delay defect test
Conventional transition delay tests target the easiest sensitisable path between two flipflops. As displayed in the figure below, there are three possible paths (Path1, Path2 and Path3) to detect the slow-to-rise or slow-to-fall faults at the mentioned location by cross mark. In the conventional Transition fault model, the ATPG tool will target the easiest sensitisable path which is Path3. This Path3 has maximum timing slack compared to others, while Path1 has minimum timing slack. So any possible physical defect on Path1 can create failure, which will not be detected by conventional Transition fault model. This results in possible test escape at small-scale CMOS technology nodes, where smaller delays can result in timing failure. The small delay defect test, targets the path of each nodes between the two flipflops having smallest timing slack. In figure 4, one will note that the small delay defect will target Path1 having smallest timing slack. This method can help avoid possible test escapes due to timing failure. A study says that more than 60% of delay defects would be occurred due to smaller delay defect as the technology shrinks.

Figure 4: The small delay defect will target Path1 having smallest timing slack.

Iddq test
Iddq tests help to measure the quiescent current. Sometimes the physical defects like gate-oxide short can result in very high leakage current. Such types of physical defects cannot be modelled properly with the help of Single Stuck-at fault model. Apart from that, the logic inside the design is intentionally kept as a non-scannable. Due to this, the conventional ATPG test cannot target those faults. Iddq can detect defects with high coverage in fewer patterns compared to Stuck-at test. It can even detect faults that remain undetected after stuck-at tests.

Figure 5: Iddq can detect defects with high coverage in fewer patterns compared to Stuck-at test.

One can achieve high defect coverage with the help of various fault models, that in turn reduce possible testability escapes. This approach also results in lower DPPM (Defective Part Per Million) after field tests. The Williams and Brown equation for the DPPM can be given as below,

D = (1 – Y^ (1-C)), where
D = Defect rate, DPPM = D * 10^6
Y = Yield, 0 < Y < 1
C = Defect coverage, 0 < C < 1
 • Based on the above equation, DPPM would be '0' for 100% coverage on any yield.
 • DPPM = 10^6 for 0% coverage on zero yield.
 • DPPM = > 200 for 99% coverage on 70% yield.

Achieving high defect coverage becomes necessary with the small-scale CMOS technology nodes. With the reduction in the size of the CMOS device, various physical defects can occur which remain undetected with the help of conventional tests. Any possible test escape in the test strategy can result in failures in the field or during system level testing, thus contributing to high DPPM. Such types of test escapes can prove to be extremely costly and unfavourable to chip manufacturers and the service industry. To avoid such situations, better test strategies need to be developed to target various faults. Applying various test vectors of various fault models can be a better solution for test quality improvement. One can take advantages of all fault models and achieve high defect coverage in the process too.

About the authors
Parth Rao, Chintan Panchal, Harsh Parikh and Ankit Shah are engineers at eInfochips.

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